Keyword : VHDL


HDLs Modeling Technique for Burst-Mode and Extended Burst-Mode Asynchronous Circuits
Jung-Lin YANG Jau-Cheng WEI Shin-Nung LU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/12/01
Vol. E93-A  No. 12 ; pp. 2590-2599
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
asynchronousburst-modeextended burst-modeHDLhandshake packageVHDLVerilogself-timed
 Summary | Full Text:PDF(1.6MB)

A Flexible Architecture for Digital Signal Processing
Wichai BOONKUMKLAO Yoshikazu MIYANAGA Kobchai DEJHAN 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2003/10/01
Vol. E86-D  No. 10 ; pp. 2179-2186
Type of Manuscript:  PAPER
Category: VLSI Systems
Keyword: 
FRMPCAreconfigurable architectureIPVHDL
 Summary | Full Text:PDF(1.3MB)

An Algorithm and a Flexible Architecture for Fast Block-Matching Motion Estimation
Jinku CHOI Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/12/01
Vol. E85-A  No. 12 ; pp. 2603-2611
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: VLSI Design
Keyword: 
motion estimationblock-matchingalgorithmarchitectureVHDL
 Summary | Full Text:PDF(587.8KB)

A Study on the Design of VME System Controller
Kang Hyeon RHEE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/06/25
Vol. E83-A  No. 6 ; pp. 1083-1090
Type of Manuscript:  Special Section PAPER (Special Section of Papers Selected from 1999 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC'99))
Category: 
Keyword: 
factory automatonVME system controllerVHDLFPGA
 Summary | Full Text:PDF(1.5MB)

Hardware Synthesis from C Programs with Estimation of Bit Length of Variables
Osamu OGAWA Kazuyoshi TAKAGI Yasufumi ITOH Shinji KIMURA Katsumasa WATANABE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/11/25
Vol. E82-A  No. 11 ; pp. 2338-2346
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
high-level synthesishardware/software codesignVHDLC languagecompiler
 Summary | Full Text:PDF(724.5KB)

A Technique for Modelling Dynamic Reconfiguration with Improved Simulation Accuracy
Milan VASILKO David CABANIS 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/11/25
Vol. E82-A  No. 11 ; pp. 2465-2474
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
logic simulationDynamically Reconfigurable Logicrun-time reconfigurationVHDLFPGAs
 Summary | Full Text:PDF(1.1MB)

Program Slicing on VHDL Descriptions and Its Evaluation
Shigeru ICHINOSE Mizuho IWAIHARA Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/12/25
Vol. E81-A  No. 12 ; pp. 2585-2594
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Design Reuse
Keyword: 
hardware description languageVHDLprogram slicingdesign reusecomponent extraction
 Summary | Full Text:PDF(853.1KB)

Combining Architectural Simulation and Behavioral Synthesis
Abderrazak JEMAI Polen KISSION Ahmed Amine JERRAYA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/10/25
Vol. E80-A  No. 10 ; pp. 1756-1766
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
architectural simulationbehavioral synthesisVHDL
 Summary | Full Text:PDF(887.4KB)

High-Level Modeling and Synthesis of Communicating Processes Using VHDL
Wayne WOLF Richard MANNO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/09/25
Vol. E76-D  No. 9 ; pp. 1039-1046
Type of Manuscript:  Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: High-Level Design
Keyword: 
high-level synthesisVHDLcontrol-dominated systems
 Summary | Full Text:PDF(737.9KB)

Integrated Design and Test Assistance for Pipeline Controllers
Hiroaki IWASHITA Tsuneo NAKATA Fumiyasu HIROSE 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/07/25
Vol. E76-D  No. 7 ; pp. 747-754
Type of Manuscript:  Special Section PAPER (Special Issue on VLSI Testing and Testable Design)
Category: 
Keyword: 
design verificationtest programVHDLRISC processor
 Summary | Full Text:PDF(600.3KB)

Functional Design of a Special Purpose Processor Based on High Level Specification Description
Hironobu KITABATAKE Katsuhiko SHIRAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/10/25
Vol. E75-A  No. 10 ; pp. 1182-1190
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
high-level synthesisASIC designVHDL
 Summary | Full Text:PDF(747.3KB)

New Trend and Future Issues of Hardware Description Language and High-Level Synthesis
Masaharu IMAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/03/25
Vol. E75-A  No. 3 ; pp. 307-313
Type of Manuscript:  INVITED PAPER (Special Section on the 4th Karuizawa Workshop on Circuits and Systems)
Category: 
Keyword: 
HDLhigh-level synthesisVHDLverilog HDLUDL/IPARTHENONSFL
 Summary | Full Text:PDF(501.8KB)