Keyword : SoC


Recent Progress of Biomedical Processor SoC for Wearable Healthcare Application: A Review
Masahiko YOSHIMOTO Shintaro IZUMI 
Publication:   
Publication Date: 2019/04/01
Vol. E102-C  No. 4 ; pp. 245-259
Type of Manuscript:  INVITED PAPER (Special Section on Solid-State Circuit Design — Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
healthcarelow-powerSoCwearable
 Summary | Full Text:PDF(2.3MB)

A 11.3-µA Physical Activity Monitoring System Using Acceleration and Heart Rate
Motofumi NAKANISHI Shintaro IZUMI Mio TSUKAHARA Hiroshi KAWAGUCHI Hiromitsu KIMURA Kyoji MARUMOTO Takaaki FUCHIKAMI Yoshikazu FUJIMORI Masahiko YOSHIMOTO 
Publication:   
Publication Date: 2018/04/01
Vol. E101-C  No. 4 ; pp. 233-242
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design — Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
adaptive samplingnormally off computingphysical activity classificationsensor fusionSoC
 Summary | Full Text:PDF(2.4MB)

Analog and Digital Collaborative Design Techniques for Wireless SoCs
Ryuichi FUJIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/02/01
Vol. E99-A  No. 2 ; pp. 514-522
Type of Manuscript:  INVITED PAPER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
wirelessSoCISDB-T1-segmant broadcastingTransferJetWireless LANspurious signaldigital pre-distortionmismatch calibrationlow power consumption
 Summary | Full Text:PDF(3.3MB)

Parallelism Analysis of H.264 Decoder and Realization on a Coarse-Grained Reconfigurable SoC
Gugang GAO Peng CAO Jun YANG Longxing SHI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/08/01
Vol. E96-D  No. 8 ; pp. 1654-1666
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Application
Keyword: 
coarse-grained reconfigurable arraySoCREMUS-IIH.264 decodermapping strategyhybrid partitioningsub-MB parallelism
 Summary | Full Text:PDF(1.6MB)

A Small-Area and Low-Power SoC for Less-Invasive Pressure Sensing Capsules in Ambulatory Urodynamic Monitoring
Hirofumi IWATO Keishi SAKANUSHI Yoshinori TAKEUCHI Masaharu IMAI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/04/01
Vol. E95-C  No. 4 ; pp. 487-494
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
pressure sensingurinary bladderSoClow powerASIP
 Summary | Full Text:PDF(1.3MB)

Impact of Self-Heating in Wire Interconnection on Timing
Toshiki KANAMOTO Takaaki OKUMURA Katsuhiro FURUKAWA Hiroshi TAKAFUJI Atsushi KUROKAWA Koutaro HACHIYA Tsuyoshi SAKATA Masakazu TANAKA Hidenari NAKASHIMA Hiroo MASUDA Takashi SATO Masanori HASHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/03/01
Vol. E93-C  No. 3 ; pp. 388-392
Type of Manuscript:  BRIEF PAPER
Category: 
Keyword: 
interconnectdelay variationparasitic resistancethermaltemperatureself-heatSoC
 Summary | Full Text:PDF(221.9KB)

Multi-Core/Multi-IP Technology for Embedded Applications
Naohiko IRIE Toshihiro HATTORI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/10/01
Vol. E92-C  No. 10 ; pp. 1232-1239
Type of Manuscript:  INVITED PAPER (Special Section on Hardware and Software Technologies on Advanced Microprocessors)
Category: 
Keyword: 
SoCmulti-coreembedded systemplatform
 Summary | Full Text:PDF(2MB)

Shared Write-Selection Transistor Cell and Leakage-Replication Read Scheme for Large Capacity MRAM Macros
Ryusuke NEBASHI Noboru SAKIMURA Tadahiko SUGIBAYASHI Naoki KASAI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/04/01
Vol. E92-C  No. 4 ; pp. 417-422
Type of Manuscript:  Special Section PAPER (Special Section on Low-Leakage, Low-Voltage, Low-Power and High-Speed Technologies for System LSIs in Deep-Submicron Era)
Category: 
Keyword: 
MRAMembedded memorySoCsystem LSI
 Summary | Full Text:PDF(579.7KB)

A Continuous-Adaptive DDRx Interface with Flexible Round-Trip-Time and Full Self Loop-Backed AC Test
Masaru HARAGUCHI Tokuya OSAWA Akira YAMAZAKI Chikayoshi MORISHIMA Toshinori MORIHARA Yoshikazu MOROOKA Yoshihiro OKUNO Kazutami ARIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/04/01
Vol. E92-C  No. 4 ; pp. 453-459
Type of Manuscript:  Special Section PAPER (Special Section on Low-Leakage, Low-Voltage, Low-Power and High-Speed Technologies for System LSIs in Deep-Submicron Era)
Category: 
Keyword: 
DDR interfaceSoCround-trip-timeloop-backed test
 Summary | Full Text:PDF(2.1MB)

A Parallel Method to Extract Critical Areas of Net Pairs for Diagnosing Bridge Faults
Keiichi SUEMITSU Toshiaki ITO Toshiki KANAMOTO Masayuki TERAI Satoshi KOTANI Shigeo SAWADA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/12/01
Vol. E91-A  No. 12 ; pp. 3524-3530
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
IDDQSoCIFAparallel execution
 Summary | Full Text:PDF(701.9KB)

Effective Domain Partitioning for Multi-Clock Domain IP Core Wrapper Design under Power Constraints
Thomas Edison YU Tomokazu YONEDA Danella ZHAO Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/03/01
Vol. E91-D  No. 3 ; pp. 807-814
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
multi-clock domainwrapper designSoCembedded core testtest scheduling
 Summary | Full Text:PDF(796.2KB)

GDME: Grey Relational Clustering Applied to a Clock Tree Construction with Zero Skew and Minimal Delay
Chia-Chun TSAI Jan-Ou WU Trong-Yen LEE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/01/01
Vol. E91-A  No. 1 ; pp. 365-374
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
SoCclock treezero skewgrey relational clusteringDME (deferred-merge embedding)RLC delay model
 Summary | Full Text:PDF(1.6MB)

On-Chip Multi-Channel Monitoring for Analog Circuit Diagnosis in Systems-on-Chip Integration
Koichiro NOGUCHI Takushi HASHIDA Makoto NAGATA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/06/01
Vol. E90-C  No. 6 ; pp. 1189-1196
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category: 
Keyword: 
SoCanalog diagnosison-chip monitor
 Summary | Full Text:PDF(1.5MB)

Proposal of Metrics for SSTA Accuracy Evaluation
Hiroyuki KOBAYASHI Nobuto ONO Takashi SATO Jiro IWAI Hidenari NAKASHIMA Takaaki OKUMURA Masanori HASHIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/04/01
Vol. E90-A  No. 4 ; pp. 808-814
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
statistical static timing analysisstatistical max operationDFMSoC
 Summary | Full Text:PDF(1.1MB)

A Fast Characterizing Method for Large Embedded Memory Modules on SoC
Masahiko OMURA Toshiki KANAMOTO Michiko TSUKAMOTO Mitsutoshi SHIROTA Takashi NAKAJIMA Masayuki TERAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/04/01
Vol. E90-A  No. 4 ; pp. 815-822
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
characterizationmemory compilerSoCLPE
 Summary | Full Text:PDF(441.6KB)

Substrate-Noise and Random-Variability Reduction with Self-Adjusted Forward Body Bias
Yoshihide KOMATSU Koichiro ISHIBASHI Makoto NAGATA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/04/01
Vol. E90-C  No. 4 ; pp. 692-698
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies)
Category: Digital
Keyword: 
substrate noiserandom variabilityforward body biasself adjustedimpuritieslatch-upCMOSSoC
 Summary | Full Text:PDF(2.2MB)

Zero-Skew Driven Buffered RLC Clock Tree Construction
Jan-Ou WU Chia-Chun TSAI Chung-Chieh KUO Trong-Yen LEE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/03/01
Vol. E90-A  No. 3 ; pp. 651-658
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
clock treeupward propagationbuffer insertionzero skewSoC
 Summary | Full Text:PDF(1.3MB)

Si-Substrate Modeling toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design
Toshiki KANAMOTO Tatsuhiko IKEDA Akira TSUCHIYA Hidetoshi ONODERA Masanori HASHIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A  No. 12 ; pp. 3560-3568
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Interconnect
Keyword: 
substrateinterconnectresistanceinductanceSoC
 Summary | Full Text:PDF(1.4MB)

Hierarchical-Analysis-Based Fast Chip-Scale Power Estimation Method for Large and Complex LSIs
Yuichi NAKAMURA Takeshi YOSHIMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A  No. 12 ; pp. 3458-3463
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Simulation and Verification
Keyword: 
SoCpower consumptionpower estimationtoggle rate
 Summary | Full Text:PDF(724.2KB)

Impact of Intrinsic Parasitic Extraction Errors on Timing and Noise Estimation
Toshiki KANAMOTO Shigekiyo AKUTSU Tamiyo NAKABAYASHI Takahiro ICHINOMIYA Koutaro HACHIYA Atsushi KUROKAWA Hiroshi ISHIKAWA Sakae MUROMOTO Hiroyuki KOBAYASHI Masanori HASHIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A  No. 12 ; pp. 3666-3670
Type of Manuscript:  Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: Interconnect
Keyword: 
interconnectdelay variationparasitic capacitanceSoC
 Summary | Full Text:PDF(433.5KB)

Hardware Design Verification Using Signal Transitions and Transactions
Nobuyuki OHBA Kohji TAKANO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/04/01
Vol. E89-A  No. 4 ; pp. 1012-1017
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
hardware prototypinghardware debugginglogic analyzerASICSoC
 Summary | Full Text:PDF(664.1KB)

A Memory Grouping Method for Reducing Memory BIST Logic of System-on-Chips
Masahide MIYAZAKI Tomokazu YONEDA Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2006/04/01
Vol. E89-D  No. 4 ; pp. 1490-1497
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
SoCtest schedulingwrapperdesign for testmemory BIST
 Summary | Full Text:PDF(1MB)

Low-Voltage and Low-Power Logic, Memory, and Analog Circuit Techniques for SoCs Using 90 nm Technology and Beyond
Koichiro ISHIBASHI Tetsuya FUJIMOTO Takahiro YAMASHITA Hiroyuki OKADA Yukio ARIMA Yasuyuki HASHIMOTO Kohji SAKATA Isao MINEMATSU Yasuo ITOH Haruki TODA Motoi ICHIHASHI Yoshihide KOMATSU Masato HAGIWARA Toshiro TSUKADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/03/01
Vol. E89-C  No. 3 ; pp. 250-262
Type of Manuscript:  INVITED PAPER (Special Section on VLSI Design Technology in the Sub-100 nm Era)
Category: 
Keyword: 
low powerCMOSSoC90 nmlow voltagevariability
 Summary | Full Text:PDF(2.1MB)

A Method of Precise Estimation of Physical Parameters in LSI Interconnect Structures
Toshiki KANAMOTO Tetsuya WATANABE Mitsutoshi SHIROTA Masayuki TERAI Tatsuya KUNIKIYO Kiyoshi ISHIKAWA Yoshihide AJIOKA Yasutaka HORIBA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12 ; pp. 3463-3470
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Interconnect
Keyword: 
SoCinterconnectphysical parameterlow-kcapacitanceresistancelayout parasitic extraction
 Summary | Full Text:PDF(592.2KB)

Wire Length Distribution Model for System LSI
Takanori KYOGOKU Junpei INOUE Hidenari NAKASHIMA Takumi UEZONO Kenichi OKADA Kazuya MASU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12 ; pp. 3445-3452
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Interconnect
Keyword: 
wire length distributioncore utilizationSoClayout-area allocation
 Summary | Full Text:PDF(1.5MB)

77-GHz MMIC Module Design Techniques for Automotive Radar Applications
Yasushi ITOH Kazuhiko HONJO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/10/01
Vol. E88-C  No. 10 ; pp. 1939-1946
Type of Manuscript:  REVIEW PAPER
Category: 
Keyword: 
millimeter-waveMMICmoduleautomotive radar sensorMCMSiPSoCflip-chip
 Summary | Full Text:PDF(1.6MB)

Low Latency Four-Flop Synchronizer with the Handshake Interface
Suk-Jin KIM Jeong-Gun LEE Kiseon KIM 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/07/01
Vol. E88-D  No. 7 ; pp. 1460-1463
Type of Manuscript:  Special Section LETTER (Special Section on Recent Advances in Circuits and Systems--Part 1)
Category: Communications and Wireless Systems
Keyword: 
synchronizertwo-flopclock domainSoC
 Summary | Full Text:PDF(445.9KB)

A Design of Real-Time JPEG Encoder for 1.4 Mega Pixel CMOS Image Sensor SoC
Kyeong-Yuk MIN Jong-Wha CHONG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/06/01
Vol. E88-A  No. 6 ; pp. 1443-1447
Type of Manuscript:  Special Section PAPER (Special Section on Papers Selected from 2004 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2004))
Category: 
Keyword: 
CMOS image sensorencoderJPEGone-chip cameraSoC
 Summary | Full Text:PDF(1.3MB)

CMOS Radio Design for Complete Single Chip GPS SoC
Norihito SUZUKI Takahide KADOYAMA Masayuki KATAKURA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/04/01
Vol. E88-C  No. 4 ; pp. 496-501
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power LSI and Low-Power IP)
Category: Analog
Keyword: 
GPSradioCMOSSoCsubstrate coupling noiselow power
 Summary | Full Text:PDF(1012KB)

0.3-1.5 V Embedded SRAM Core with Write-Replica Circuit Using Asymmetrical Memory Cell and Source-Level-Adjusted Direct-Sense-Amplifier
Toshikazu SUZUKI Yoshinobu YAMAGAMI Ichiro HATANAKA Akinori SHIBAYAMA Hironori AKAMATSU Hiroyuki YAMAUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/04/01
Vol. E88-C  No. 4 ; pp. 630-638
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power LSI and Low-Power IP)
Category: Memory
Keyword: 
SRAMlow-voltagewide-voltageSoC
 Summary | Full Text:PDF(2.7MB)

Design and Application of Ferroelectric Memory Based Nonvolatile SRAM
Shoichi MASUI Tsuzumi NINOMIYA Takashi OHKAWA Michiya OURA Yoshimasa HORII Nobuhiro KIN Koichiro HONDA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/11/01
Vol. E87-C  No. 11 ; pp. 1769-1776
Type of Manuscript:  INVITED PAPER (Special Section on New System Paradigms for Integrated Electronics)
Category: 
Keyword: 
ferroelectric materialnonvolatile memoryprogrammingSoCprogrammable logic devices
 Summary | Full Text:PDF(1.6MB)

µI/O Architecture: A Power-Aware Interconnect Circuit Design for SoC and SiP
Yusuke KANNO Hiroyuki MIZUNO Nobuhiro OODAIRA Yoshihiko YASU Kazumasa YANAGISAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/04/01
Vol. E87-C  No. 4 ; pp. 589-597
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies)
Category: 
Keyword: 
low-costSystem-on-ChipSoCSystem-in-PackageSiPhierarchical I/O designsignal-level convertersignal wall functionlow-powerinterconnect circuit
 Summary | Full Text:PDF(967.2KB)

Routing Methodology for Minimizing Crosstalk in SoC
Takashi YAMADA Atsushi SAKAI Yoshifumi MATSUSHITA Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/09/01
Vol. E86-A  No. 9 ; pp. 2347-2356
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
SoCsignal integritycrosstalkinterconnecttiming analysis
 Summary | Full Text:PDF(1.8MB)

Pre-Route Power Analysis Techniques for SoC
Takashi YAMADA Takeshi SAKAMOTO Shinji FURUICHI Mamoru MUKUNO Yoshifumi MATSUSHITA Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/03/01
Vol. E86-A  No. 3 ; pp. 686-692
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
SoCpower analysisgate-levelcustom wire load model
 Summary | Full Text:PDF(763.6KB)

Packaging Technology Trends and Challenges for System-in-Package
Akihiro DOHYA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2001/12/01
Vol. E84-C  No. 12 ; pp. 1756-1762
Type of Manuscript:  INVITED PAPER (Special Issue on Integrated Systems with New Concepts)
Category: 
Keyword: 
packaging technologysystem-in-packageSIPSoCCSP
 Summary | Full Text:PDF(4.1MB)