Keyword : SRAM with logic gate

Redundancy Circuit for a Sub-nanosecond, Megabit ECL-CMOSSRAM
Kenichi OHHATA  Takeshi KUSUNOKI  Hiroaki NAMBU  Kazuo KANETANI  Toru MASUDA  Masayuki OHAYASHI  Satomi HAMAMOTO  Kunihiko YAMAGUCHI  Youji IDEI  Noriyuki HOMMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/03/20
Vol. E79-C  No. 3  pp. 415-423
Type of Manuscript: PAPER
Category: Integrated Electronics
Keyword: 
redundancy,  ECL-CMOS SRAM,  SRAM with logic gate,  BiCMOS, 
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