IEICE SEARCH SYSTEM

Keyword : SGT

Study of Pattern Area Reduction for Standard Cell with SGT and Planar Transistor Takahiro KODAMA Shigeyoshi WATANABE
Publication: C - Abstracts of IEICE TRANSACTIONS on Electronics (Japanese Edition) Publication Date: 2011/06/01 Vol. J94-C No. 6 pp. 166-170 Type of Manuscript: LETTER Category: Keyword: SGT, system LSI, design rule, pattern area, standard cell,
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Study of Pattern Area Reduction for System LSI with SGT and Stacked SGT Takahiro KODAMA Shigeyoshi WATANABE
Publication: C - Abstracts of IEICE TRANSACTIONS on Electronics (Japanese Edition) Publication Date: 2010/01/01 Vol. J93-C No. 1 pp. 33-34 Type of Manuscript: LETTER Category: Keyword: SGT, stacked SGT, system LSI, design rule, pattern area,
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Study of Reduction of Pattern Area for System LSI with SGT Tomohiro YOKOTA Shigeyoshi WATANABE
Publication: C - Abstracts of IEICE TRANSACTIONS on Electronics (Japanese Edition) Publication Date: 2009/09/01 Vol. J92-C No. 9 pp. 537-539 Type of Manuscript: LETTER Category: Keyword: SGT, systemLSI, NAND, pattern area, full adder,
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