Keyword : PVT variation


A 32-kHz Real-Time Clock Oscillator with On-Chip PVT Variation Compensation Circuit for Ultra-Low Power MCUs
Keishi TSUBAKI Tetsuya HIROSE Nobutaka KUROKI Masahiro NUMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2015/05/01
Vol. E98-C  No. 5 ; pp. 446-453
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
ROSCRTCoscillatorcomparatorPVT variationlow-power
 Summary | Full Text:PDF(2.2MB)

Variation-Aware Flip Flop for DVFS Applications
YoungKyu JANG Changnoh YOON Ik-Joon CHANG Jinsang KIM 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2015/05/01
Vol. E98-C  No. 5 ; pp. 439-445
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
design-for-variabilityflip-flopPVT variationDVFS
 Summary | Full Text:PDF(1.2MB)

A Fully On-Chip, 6.66-kHz, 320-nA, 56ppm/°C, CMOS Relaxation Oscillator with PVT Variation Compensation Circuit
Keishi TSUBAKI Tetsuya HIROSE Yuji OSAKI Seiichiro SHIGA Nobutaka KUROKI Masahiro NUMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2014/06/01
Vol. E97-C  No. 6 ; pp. 512-518
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category: 
Keyword: 
ROSCRTCoscillatorcomparatorPVT variationlow-power
 Summary | Full Text:PDF(2.3MB)

DFV-Aware Flip-Flops Using C-Elements
Changnoh YOON Youngmin CHO Jinsang KIM 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/07/01
Vol. E94-C  No. 7 ; pp. 1229-1232
Type of Manuscript:  BRIEF PAPER
Category: Electronic Circuits
Keyword: 
design-for-variabilityflip-flopnanometer processPVT variationsingle event upset
 Summary | Full Text:PDF(577KB)

Subthreshold SRAM with Write Assist Technique Using On-Chip Threshold Voltage Monitoring Circuit
Kei MATSUMOTO Tetsuya HIROSE Yuji OSAKI Nobutaka KUROKI Masahiro NUMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/06/01
Vol. E94-C  No. 6 ; pp. 1042-1048
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category: 
Keyword: 
SRAMthreshold voltage variationcompensation circuitprocess variationtemperature variationPVT variation
 Summary | Full Text:PDF(837.7KB)

Robust Subthreshold CMOS Digital Circuit Design with On-Chip Adaptive Supply Voltage Scaling Technique
Yuji OSAKI Tetsuya HIROSE Kei MATSUMOTO Nobutaka KUROKI Masahiro NUMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/01/01
Vol. E94-C  No. 1 ; pp. 80-88
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
subthreshold operationdigital circuitsPVT variationdelay compensation
 Summary | Full Text:PDF(910.2KB)

An On-Chip PVT Compensation Technique with Current Monitoring Circuit for Low-Voltage CMOS Digital LSIs
Yusuke TSUGITA Ken UENO Tetsuya HIROSE Tetsuya ASAI Yoshihito AMEMIYA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/06/01
Vol. E93-C  No. 6 ; pp. 835-841
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category: 
Keyword: 
digital circuitsthreshold voltage variationcompensation circuitPVT variation
 Summary | Full Text:PDF(974.1KB)

An On-Chip Supply-Voltage Control System Considering PVT Variations for Worst-Caseless Lower Voltage SoC Design
Takayuki GYOHTEN Fukashi MORISHITA Isamu HAYASHI Mako OKAMOTO Hideyuki NODA Katsumi DOSAKA Kazutami ARIMOTO Yasutaka HORIBA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/11/01
Vol. E89-C  No. 11 ; pp. 1519-1525
Type of Manuscript:  Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies)
Category: 
Keyword: 
PVT variationtemperature detectionseries regulator
 Summary | Full Text:PDF(1.5MB)

Multi-Ported Register File for Reducing the Impact of PVT Variation
Yuuichirou IKEDA Masaya SUMITA Makoto NAGATA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/03/01
Vol. E89-C  No. 3 ; pp. 356-363
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design Technology in the Sub-100 nm Era)
Category: Signal Integrity and Variability
Keyword: 
multi-ported register fileself timing circuitsPVT variationcrosstalk noise
 Summary | Full Text:PDF(1.3MB)