Keyword : PLL


An On-Chip Measurement of PLL Transfer Function and Lock Range through Fully Digital Interface
Toshiyuki KIKKAWA Toru NAKURA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2016/02/01
Vol. E99-C  No. 2 ; pp. 275-284
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
PLLtransfer functionlock rangeon-chip measurement
 Summary | Full Text:PDF(1.1MB)

Radiation-Hardened PLL with a Switchable Dual Modular Redundancy Structure
SinNyoung KIM Akira TSUCHIYA Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2014/04/01
Vol. E97-C  No. 4 ; pp. 325-331
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design,---,Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
radiation-hardened phase-locked loop (RH-PLL)PLLradiation-hardened-by-design (RHBD)dual modular redundancy (DMR)
 Summary | Full Text:PDF(3.8MB)

Injection Locked Charge-Pump PLL with a Replica of the Ring Oscillator
Jeonghoon HAN Masaya MIYAHARA Akira MATSUZAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2014/04/01
Vol. E97-C  No. 4 ; pp. 316-324
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design,---,Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
Injection-lockring oscillatorlock rangePLL
 Summary | Full Text:PDF(2.8MB)

Wide Frequency-Range Spread-Spectrum Clock Generator with Digital Modulation Control
Takashi KAWAMOTO Masato SUZUKI Takayuki NOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2013/06/01
Vol. E96-C  No. 6 ; pp. 935-941
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
spread-spectrum clock generatorPLLVCOmulti-modulus divider
 Summary | Full Text:PDF(2.3MB)

Low Pass Filter-Less Pulse Width Controlled PLL Using Time to Soft Thermometer Code Converter
Toru NAKURA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/02/01
Vol. E95-C  No. 2 ; pp. 297-302
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
PLLPWCOpulse width controlsoft thermometer codeLPF-lessquantization noise free
 Summary | Full Text:PDF(1.3MB)

A Single-Chip RF Tuner/OFDM Demodulator for Mobile Digital TV Application
Yoshimitsu TAKAMATSU Ryuichi FUJIMOTO Tsuyoshi SEKINE Takaya YASUDA Mitsumasa NAKAMURA Takuya HIRAKAWA Masato ISHII Motohiko HAYASHI Hiroya ITO Yoko WADA Teruo IMAYAMA Tatsuro OOMOTO Yosuke OGASAWARA Masaki NISHIKAWA Yoshihiro YOSHIDA Kenji YOSHIOKA Shigehito SAIGUSA Hiroshi YOSHIDA Nobuyuki ITOH 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/04/01
Vol. E94-C  No. 4 ; pp. 557-566
Type of Manuscript:  Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration)
Category: 
Keyword: 
digital TV1-segment broadcastingISDB-Ttunablelow-noise amplifierspurious signalprescalerPLL
 Summary | Full Text:PDF(3MB)

A 60-GHz Phase-Locked Loop with Inductor-Less Wide Operation Range Prescaler in 90-nm CMOS
Hiroaki HOSHINO Ryoichi TACHIBANA Toshiya MITOMO Naoko ONO Yoshiaki YOSHIHARA Ryuichi FUJIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/06/01
Vol. E92-C  No. 6 ; pp. 785-791
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category: 
Keyword: 
PLLsynthesizerVCOILFDphase noise
 Summary | Full Text:PDF(594.1KB)

Digital-Centric RF CMOS Technologies
Akira MATSUZAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/11/01
Vol. E91-C  No. 11 ; pp. 1720-1725
Type of Manuscript:  INVITED PAPER (Special Section on Microwave and Millimeter-wave Technologies)
Category: 
Keyword: 
CMOSRFanalogdigitaltunerPLLsamplingmixerwireless
 Summary | Full Text:PDF(880.1KB)

A Novel Open Loop Structure for Phase Shifting and Frequency Synthesizing
Sarang KAZEMINIA Khayrollah HADIDI Abdollah KHOEI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/02/01
Vol. E91-A  No. 2 ; pp. 491-496
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
phase shifterfrequency synthesizerfrequency multiplierDLLPLL
 Summary | Full Text:PDF(490.6KB)

A Low-Power Low-Noise Clock Signal Generator for Next-Generation Mobile Wireless Terminals
Akihide SAI Daisuke KUROSE Takafumi YAMAJI Tetsuro ITAKURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/02/01
Vol. E91-A  No. 2 ; pp. 557-560
Type of Manuscript:  Special Section LETTER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
clock generatorjitterPLLAnalog-to-Digital Converter (ADC)
 Summary | Full Text:PDF(384.1KB)

Miller Capacitor with Wide Input Range and Its Application to PLL Loop Filter
Masahiro YOSHIOKA Nobuo FUJII 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A  No. 12 ; pp. 3685-3692
Type of Manuscript:  PAPER
Category: Analog Signal Processing
Keyword: 
Miller capacitorPLLlow frequency filterloop filter
 Summary | Full Text:PDF(830.7KB)

Spread-Spectrum Clock Generator for Serial ATA with Multi-Bit ΣΔ Modulator-Controlled Fractional PLL
Masaru KOKUBO Takashi KAWAMOTO Takashi OSHIMA Takayuki NOTO Masato SUZUKI Shigeyuki SUZUKI Takashi HAYASAKA Tomoaki TAKAHASHI Jun KASAI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/11/01
Vol. E89-C  No. 11 ; pp. 1682-1688
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
PLLspread-spectrumjitterserial ATA
 Summary | Full Text:PDF(769KB)

A Very Low Power 10 MHz CMOS Continuous-Time Bandpass Filter with On-Chip Automatic Tuning
Gholamreza Zareh FATIN Mohammad GHADAMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/07/01
Vol. E89-C  No. 7 ; pp. 1089-1096
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
bandpass filterGm-Cquality factordynamic rangeIM3automatic tuningPLL
 Summary | Full Text:PDF(667.6KB)

All Digital Dividing Ratio Changeable PLL Using Delay Clock Pulse with Low Jitter
Mitsutoshi YAHARA Kuniaki FUJIMOTO Hirofumi SASAKI Takashi SHIBUYA Yoshinori HIGASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/06/01
Vol. E89-A  No. 6 ; pp. 1527-1532
Type of Manuscript:  Special Section PAPER (Special Section on Papers Selected from 2005 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2005))
Category: 
Keyword: 
PLLjitterdelay clocklock-in rangedigital
 Summary | Full Text:PDF(653.3KB)

An Efficient Approach to Build Accurate Behavioral Models of PLL Designs
Chin-Cheng KUO Yu-Chien WANG Chien-Nan Jimmy LIU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/02/01
Vol. E89-A  No. 2 ; pp. 391-398
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
analog behavioral modelPLLIPbottom-up extraction
 Summary | Full Text:PDF(799.8KB)

An Effective Built-In Self-Test for Chargepump PLL
Junseok HAN Dongsup SONG Hagbae KIM YoungYong KIM Sungho KANG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/08/01
Vol. E88-C  No. 8 ; pp. 1731-1733
Type of Manuscript:  Special Section LETTER (Special Section on Papers Selected from AP-ASIC 2004)
Category: 
Keyword: 
mixed-signal testBISTPLL
 Summary | Full Text:PDF(559.7KB)

A Spread Spectrum Clock Generator Using Digital Tracking Scheme
Takefumi YOSHIKAWA Tsuyoshi EBUCHI Yukio ARIMA Toru IWATA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/06/01
Vol. E88-C  No. 6 ; pp. 1288-1289
Type of Manuscript:  Special Section LETTER (Special Section on Analog Circuit and Device Technologies)
Category: PLL
Keyword: 
PLLspread spectrum clockingEMIphase interpolator
 Summary | Full Text:PDF(594.1KB)

A GFSK Transmitter Architecture for a Bluetooth RF-IC, Featuring a Variable-Loop-Bandwidth Phase-Locked Loop Modulator
Masaru KOKUBO Takashi OSHIMA Katsumi YAMAMOTO Kunio TAKAYASU Yoshiyuki EZUMI Shinya AIZAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/03/01
Vol. E88-C  No. 3 ; pp. 385-394
Type of Manuscript:  PAPER
Category: Microwaves, Millimeter-Waves
Keyword: 
FSKmodulatordelta-sigmaPLLvariable loop bandwidthBluetooth
 Summary | Full Text:PDF(1.7MB)

A Fast-Lock DLL with Power-On Reset Circuit
Kuo-Hsing CHENG Yu-Lung LO Shu-Yu JIANG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/09/01
Vol. E87-A  No. 9 ; pp. 2210-2220
Type of Manuscript:  Special Section PAPER (Special Section on Nonlinear Theory and its Applications)
Category: 
Keyword: 
DLLPLLPORfast lockmultiphase outputs
 Summary | Full Text:PDF(1.2MB)

A Clock and Data Recovery PLL for Variable Bit Rate NRZ Data Using Adaptive Phase Frequency Detector
Gijun IDEI Hiroaki KUNIEDA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/06/01
Vol. E87-C  No. 6 ; pp. 956-963
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit and Device Technologies)
Category: 
Keyword: 
capture rangeCCOCDRclock and data recoveryfalse lockjitterNRZPFDPLLVCOz-domain analysis
 Summary | Full Text:PDF(1.8MB)

A Design of Compact PLL with Adaptive Active Loop Filter Circuit
Shiro DOSHO Naoshi YANAGISAWA Masaomi TOYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/06/01
Vol. E87-C  No. 6 ; pp. 949-955
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit and Device Technologies)
Category: 
Keyword: 
PLLadaptive biasingLPFcompact0.15 µm-CMOS
 Summary | Full Text:PDF(750.5KB)

A 2.4-GHz PLL Synthesizer for a 1-V Bluetooth RF Transceiver
Akihiro YAMAGISHI Mamoru UGAJIN Tsuneo TSUKAHARA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/06/01
Vol. E87-C  No. 6 ; pp. 895-900
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit and Device Technologies)
Category: 
Keyword: 
PLLsynthesizerlow-powerphase noiseBluetooth
 Summary | Full Text:PDF(741.7KB)

Novel 622 Mb/s Burst-Mode Clock and Data Recovery Circuits with Muxed Oscillators
Yu-Gun KIM Chun-Oh LEE Seung-Woo LEE Hyun-Su CHAI Hyun-Suk RYU Woo-Young CHOI 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2003/11/01
Vol. E86-B  No. 11 ; pp. 3288-3292
Type of Manuscript:  LETTER
Category: Communication Devices/Circuits
Keyword: 
burst-modePLLCDRPON
 Summary | Full Text:PDF(1.1MB)

A New Phase Detector Scheme for Reducing Jitter in Clock Recovery Circuits
Kang-Yoon LEE Deog-Kyoon JEONG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2003/02/01
Vol. E86-C  No. 2 ; pp. 224-228
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
phase detectorjitterclock recoveryPLL
 Summary | Full Text:PDF(245.1KB)

Low Supply Voltage and Low-Power 1-GHz PLL Frequency Synthesizer for Mobile Terminals
Masaru KOKUBO Yoshiyuki SHIBAHARA Hirokazu AOKI Changku HWANG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2003/01/01
Vol. E86-C  No. 1 ; pp. 71-78
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
PLLVCOcharge-pumpdynamic output stagestability
 Summary | Full Text:PDF(1.5MB)

A 0.7-V 200-MHz Self-Calibration PLL
Yoshiyuki SHIBAHARA Masaru KOKUBO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/08/01
Vol. E85-C  No. 8 ; pp. 1577-1580
Type of Manuscript:  Special Section PAPER (Special Issue on High-Performance Analog Integrated Circuits)
Category: 
Keyword: 
PLLVCOcalibrationleakage currentlow voltage
 Summary | Full Text:PDF(1MB)

A Phase Lock Detector for 16-QAM Systems for High-Speed Wireless Communications
Myung Sup KIM Jin Suk SEONG Doeck Gil OH 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2002/03/01
Vol. E85-B  No. 3 ; pp. 658-662
Type of Manuscript:  LETTER
Category: Wireless Communication Technology
Keyword: 
wirelessPLLcarrierphaselock and detection
 Summary | Full Text:PDF(302.2KB)

A Dynamically Phase Adjusting PLL for Improvement of Lock-up Performance
Takeo YASUDA Hiroaki FUJITA Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Vol. E84-A  No. 11 ; pp. 2793-2801
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Analog Design
Keyword: 
PLLphase adjustvariable delaylock-up
 Summary | Full Text:PDF(1.4MB)

Techniques for Widening Lock and Pull-in Ranges and Suppressing Jitter in Clock and Data Recovery ICs--Duplicated Loop Control CDR--
Keiji KISHINE Noboru ISHIHARA Haruhiko ICHINO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2001/04/01
Vol. E84-C  No. 4 ; pp. 460-469
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
clock and data recoveryPLLduplicated looplow jitter2.5-Gb/s
 Summary | Full Text:PDF(1MB)

A 3.3 V CMOS PLL with a Self-Feedback VCO
Yeon Kug MOON Kwang Sub YOON 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/12/25
Vol. E83-A  No. 12 ; pp. 2623-2626
Type of Manuscript:  Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: Analog Circuit Design
Keyword: 
PLLself-feedback VCOCMOSDC-DC voltage up/down converter
 Summary | Full Text:PDF(791.1KB)

High-Speed Wide-Locking Range VCO with Frequency Calibration
Takeo YASUDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/12/25
Vol. E83-A  No. 12 ; pp. 2616-2622
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Analog Circuit Design
Keyword: 
VCOPLLhigh speedwide locking rangecalibration
 Summary | Full Text:PDF(1.4MB)

Load Leveling Using EDLCs under PLL Control
Goichi ARIYOSHI Katsuaki MURATA Koosuke HARADA Kiyomi YAMASAKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/06/25
Vol. E83-A  No. 6 ; pp. 1014-1022
Type of Manuscript:  Special Section PAPER (Special Section of Papers Selected from 1999 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC'99))
Category: 
Keyword: 
load levelingenergy storagePLLbi-directionalelectric double-layer capacitor
 Summary | Full Text:PDF(2MB)

A 1.0 Gbps CMOS Oversampling Data Recovery Circuit with Fine Delay Generation Method
Jun-Young PARK Jin-Ku KANG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/06/25
Vol. E83-A  No. 6 ; pp. 1100-1105
Type of Manuscript:  Special Section PAPER (Special Section of Papers Selected from 1999 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC'99))
Category: 
Keyword: 
oversampling data recoveryPLLDLLjitter
 Summary | Full Text:PDF(1.4MB)

A High-Speed, Low-Power Phase Frequency Detector and Charge-Pump Circuits for High Frequency Phase-Locked Loops
Won-Hyo LEE Sung-Dae LEE Jun-Dong CHO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/11/25
Vol. E82-A  No. 11 ; pp. 2514-2520
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
PFDcharge-pumplow powerPLLhigh speedD flip-floperror detection range
 Summary | Full Text:PDF(807.5KB)

High-Speed, Low-Power Lightwave Communication ICs Using InP/InGaAs Double-Heterojunction Bipolar Transistors
Eiichi SANO Kenji KURISHIMA Hiroki NAKAJIMA Shoji YAMAHATA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/11/25
Vol. E82-C  No. 11 ; pp. 2000-2006
Type of Manuscript:  Special Section PAPER (Special Issue on High-Frequency/High-Speed Devices for Information and Communication Systems in the 21st Century)
Category: Low Power-Consumption RF ICs
Keyword: 
InPHBTamplifierflip-flopPLL
 Summary | Full Text:PDF(1.7MB)

A 0.25 µm CMOS/SIMOX PLL Clock Generator Embedded in a Gate Array LSI with a Locking Range of 5 to 500 MHz
Hiroki SUTOH Kimihiro YAMAKOSHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/07/25
Vol. E82-C  No. 7 ; pp. 1334-1340
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
PLLCMOS/SIMOXVCOclockjitterskewlock range
 Summary | Full Text:PDF(2MB)

Low-Power 2.5-Gb/s Si-Bipolar IC Chipset for Optical Receivers and Transmitters Using Low-Voltage and Adjustment-Free Circuit Techniques
Masaki HIROSE Keiji KISHINE Haruhiko ICHINO Noboru ISHIHARA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/03/25
Vol. E82-C  No. 3 ; pp. 511-518
Type of Manuscript:  Special Section PAPER (Special Issue on Ultra-High-Speed IC and LSI Technology)
Category: Silicon Devices
Keyword: 
optical receiveroptical transmitteradjustment freeSi bipolaroffsetPLL
 Summary | Full Text:PDF(1.1MB)

Low Voltage/Low Power CMOS VCO
Changku HWANG Masaru KOKUBO Hirokazu AOKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/03/25
Vol. E82-A  No. 3 ; pp. 424-430
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 11th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
microprocessorPLLV-I convertercurrent and voltage controlled oscillator (CCO and VCO)
 Summary | Full Text:PDF(402.8KB)

Dual-Loop Digital PLL Design for Adaptive Clock Recovery
Tae Hun KIM Beomsup KIM 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/12/25
Vol. E81-A  No. 12 ; pp. 2509-2514
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Transistor-level Circuit Analysis, Design and Verification
Keyword: 
digital PLLDPLLPLLadaptive algorithmclock recovery
 Summary | Full Text:PDF(638.8KB)

The Phase Locked Loop for Clock Recovery Used in a Single-Chip 4-Channel 155Mb/s CMOS ATM Physical Layer Controller LSI
Takehiko NAKAO Masanori KUWAHARA Yasuo OHARA Reiji ARIYOSHI Toshihiko KITAZUME Naoki SUGAWA Takeshi OGAWARA Satoshi ODA Shoji NOMURA Yuichi MIYAZAWA Akira KANUMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/05/25
Vol. E81-C  No. 5 ; pp. 746-749
Type of Manuscript:  Special Section LETTER (Special Issue on Multimedia, Network, and DRAM LSIs)
Category: 
Keyword: 
PLLjitterATMQPLC
 Summary | Full Text:PDF(277.6KB)

Performance Evaluation for Vehicular Speed Response Phase Locked Loop in Ricean Fading Environment
Masanori HAMAMURA Shin'ichi TACHIKAWA 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 1998/03/25
Vol. E81-B  No. 3 ; pp. 609-615
Type of Manuscript:  PAPER
Category: Radio Communication
Keyword: 
mobile communicationRicean fadingmillimeter wavePLLQPSKfrequency offsetirreducible bit error rate
 Summary | Full Text:PDF(429.3KB)

Optimal Loop Bandwidth Design for Low Noise PLL Applications
Kyoohyun LIM Seung Hee CHOI Beomsup KIM 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/10/25
Vol. E80-A  No. 10 ; pp. 1979-1985
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
optimal bandwidthPLLjitterlow noise
 Summary | Full Text:PDF(555.3KB)

A Low Power 622MHz CMOS Phase-Locked Loop with Source Coupled VCO and Dynamic PFD
Hiroyasu YOSHIZAWA Kenji TANIGUCHI Hiroyuki SHIRAHAMA Kenichi NAKASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/06/25
Vol. E80-A  No. 6 ; pp. 1015-1020
Type of Manuscript:  Special Section PAPER (Special Section of Papers Selected from 1996 International Technical Conference on Circuits/Systems, Computers and Communications(ITC-CSCC'96))
Category: 
Keyword: 
PLLPFDVCOlow powersource couplingdynamic circuit
 Summary | Full Text:PDF(516.8KB)

Experiments of Secure Communications Via Chaotic Synchronization of Phase-Locked Loops
Atsushi SATO Tetsuro ENDO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/10/25
Vol. E78-A  No. 10 ; pp. 1286-1290
Type of Manuscript:  Special Section PAPER (Special Section on Nonlinear Theory and Its Applications)
Category: 
Keyword: 
secure communication systemPLLchaotic synchronization2-channel method
 Summary | Full Text:PDF(372.3KB)

Calculation of Harmonic Distortion of PLL FM Demodulator with Time Delay
Yutaka TAKAHASHI Hitoshi SAKAGAMI 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 1995/09/25
Vol. E78-B  No. 9 ; pp. 1336-1338
Type of Manuscript:  LETTER
Category: Communication Systems and Transmission Equipment
Keyword: 
PLLdistortiondelaydemodulator
 Summary | Full Text:PDF(192.8KB)

A 1.5-V 250-MHz to 3.0-V 622-MHz Operation CMOS Phase-Locked Loop with Precharge Type Phase-Frequency Detector
Harufusa KONDOH Hiromi NOTANI Tsutomu YOSHIMURA Hiroshi SHIBATA Yoshio MATSUDA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/04/25
Vol. E78-C  No. 4 ; pp. 381-388
Type of Manuscript:  Special Section PAPER (Special Issue on Low-Voltage, Low-Power Integrated Circuits)
Category: Digital Circuits
Keyword: 
PLLPFDVCOCMOSATM
 Summary | Full Text:PDF(672.1KB)

A PLL-Based Programmable Clock Generator with 50-to 350-MHz Oscillating Range for Video Signal Processors
Junichi GOTO Masakazu YAMASHINA Toshiaki INOUE Benjamin S. SHIH Youichi KOSEKI Tadahiko HORIUCHI Nobuhisa HAMATAKE Kouichi KUMAGAI Tadayoshi ENOMOTO Hachiro YAMADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/12/25
Vol. E77-C  No. 12 ; pp. 1951-1956
Type of Manuscript:  Special Section PAPER (Special Issue on Multimedia, Analog and Processing LSIs)
Category: Processor Interfaces
Keyword: 
electronic circuitsclock generatorPLLfrequency multiplicationVCOVCO gainjitterpull-in rangeCMOSVSP
 Summary | Full Text:PDF(691.7KB)

A Study of a MOS VCO Circuit by Using a Current–Controlled Differential Delay Cell
Yasuhiro SUGIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/11/25
Vol. E77-A  No. 11 ; pp. 1929-1931
Type of Manuscript:  Special Section LETTER (Special Section of Letters Selected from the 1994 IEICE Spring Conference)
Category: 
Keyword: 
MOS analog circuitPLLVCOcurrent controldifferential delay cell
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The Homoclinic Points and Chaos from Phase–Locked Loops with Large Damping
Tetsuro ENDO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/11/25
Vol. E77-A  No. 11 ; pp. 1764-1770
Type of Manuscript:  Special Section PAPER (Special Section on Nonlinear Theory and Its Applications)
Category: Analysis of Phase Locked Loops
Keyword: 
PLLchaos homoclinic pointsMelnikov methodlarge damping
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High Speed DRAMs with Innovative Architectures
Shigeo OHSHIMA Tohru FURUYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/08/25
Vol. E77-C  No. 8 ; pp. 1303-1315
Type of Manuscript:  INVITED PAPER (Special Section on High Speed and High Density Multi Functional LSI Memories)
Category: DRAM
Keyword: 
DRAMmemory bottleneckdata bandwidthlatencysynchronous DRAMpipeline architecturedata prefetchingcache DRAMfast copybackRambus interfaceRambus DRAMprotocol packetPLL
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Computer Simulation of Jitter Characteristics of PLL for Arbitrary Data and Jitter Patterns
Kenichi NAKASHI Hiroyuki SHIRAHAMA Kenji TANIGUCHI Osamu TSUKAHARA Tohru EZAKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/06/25
Vol. E77-A  No. 6 ; pp. 977-984
Type of Manuscript:  Special Section PAPER (Special Section of Papers Selected from 1993 Joint Technical Conference on Circuits/Systems, Computers and Communications (JTC-CSCC'93))
Category: Analog Circuits and Signal Processing
Keyword: 
PLLjittertime-domain simulationphase detectorNRZretiming
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A Self Frequency Preset PLL Synthesizer
Kazuhiko SEKI Shuzo KATO 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 1993/05/25
Vol. E76-B  No. 5 ; pp. 473-479
Type of Manuscript:  Special Section PAPER (Special Issue on Satellite Communications Networking and Applications)
Category: 
Keyword: 
PLLsynthesizerpresetTDMAfrequency hopping
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High Resolution and Fast Frequency Settling PLL Synthesizer
Kazuhiko SEKI Masahiro MORIKURA Shuzo KATO 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 1992/08/25
Vol. E75-B  No. 8 ; pp. 739-746
Type of Manuscript:  Special Section PAPER (Special Issue on the 4th Japan-Korea Joint Conference on Communications, Networks, Switching Systems and Satellite Communications (4th JC-CNSS))
Category: 
Keyword: 
PLLsynthesizerDDSTDMAfrequency hopping
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A Fully Integrated 6.25% Pull-in Range Digital PLL for ISDN Primary Rate Interface LSI
Harufusa KONDOH Seiji KOZAKI Shinya MAKINO Hiromi NOTANI Fuminobu HIDANI Masao NAKAYA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1992/03/25
Vol. E75-C  No. 3 ; pp. 280-287
Type of Manuscript:  Special Section PAPER (Special Issue on Analog LSI and Related Technology)
Category: 
Keyword: 
PLLpull-in rangeoscillatorISDNprimary rate interface
 Summary | Full Text:PDF(636.3KB)