Keyword : PFD


A Clock and Data Recovery PLL for Variable Bit Rate NRZ Data Using Adaptive Phase Frequency Detector
Gijun IDEI Hiroaki KUNIEDA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/06/01
Vol. E87-C  No. 6 ; pp. 956-963
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit and Device Technologies)
Category: 
Keyword: 
capture rangeCCOCDRclock and data recoveryfalse lockjitterNRZPFDPLLVCOz-domain analysis
 Summary | Full Text:PDF(1.8MB)

A 3.3 V CMOS Dual-Looped PLL with a Current-Pumping Algorithm
Hyuk-Jun SUNG Kwang Sub YOON 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/02/25
Vol. E83-A  No. 2 ; pp. 267-271
Type of Manuscript:  Special Section LETTER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
dual-looped PLLPFDVCOV-I convertercurrent-pumping algorithm
 Summary | Full Text:PDF(514KB)

A High-Speed, Low-Power Phase Frequency Detector and Charge-Pump Circuits for High Frequency Phase-Locked Loops
Won-Hyo LEE Sung-Dae LEE Jun-Dong CHO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/11/25
Vol. E82-A  No. 11 ; pp. 2514-2520
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
PFDcharge-pumplow powerPLLhigh speedD flip-floperror detection range
 Summary | Full Text:PDF(807.5KB)

A Low Power 622MHz CMOS Phase-Locked Loop with Source Coupled VCO and Dynamic PFD
Hiroyasu YOSHIZAWA Kenji TANIGUCHI Hiroyuki SHIRAHAMA Kenichi NAKASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/06/25
Vol. E80-A  No. 6 ; pp. 1015-1020
Type of Manuscript:  Special Section PAPER (Special Section of Papers Selected from 1996 International Technical Conference on Circuits/Systems, Computers and Communications(ITC-CSCC'96))
Category: 
Keyword: 
PLLPFDVCOlow powersource couplingdynamic circuit
 Summary | Full Text:PDF(516.8KB)

A 1.5-V 250-MHz to 3.0-V 622-MHz Operation CMOS Phase-Locked Loop with Precharge Type Phase-Frequency Detector
Harufusa KONDOH Hiromi NOTANI Tsutomu YOSHIMURA Hiroshi SHIBATA Yoshio MATSUDA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/04/25
Vol. E78-C  No. 4 ; pp. 381-388
Type of Manuscript:  Special Section PAPER (Special Issue on Low-Voltage, Low-Power Integrated Circuits)
Category: Digital Circuits
Keyword: 
PLLPFDVCOCMOSATM
 Summary | Full Text:PDF(672.1KB)