Keyword : NRZ


A Clock and Data Recovery PLL for Variable Bit Rate NRZ Data Using Adaptive Phase Frequency Detector
Gijun IDEI Hiroaki KUNIEDA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/06/01
Vol. E87-C  No. 6 ; pp. 956-963
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit and Device Technologies)
Category: 
Keyword: 
capture rangeCCOCDRclock and data recoveryfalse lockjitterNRZPFDPLLVCOz-domain analysis
 Summary | Full Text:PDF(1.8MB)

Computer Simulation of Jitter Characteristics of PLL for Arbitrary Data and Jitter Patterns
Kenichi NAKASHI Hiroyuki SHIRAHAMA Kenji TANIGUCHI Osamu TSUKAHARA Tohru EZAKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/06/25
Vol. E77-A  No. 6 ; pp. 977-984
Type of Manuscript:  Special Section PAPER (Special Section of Papers Selected from 1993 Joint Technical Conference on Circuits/Systems, Computers and Communications (JTC-CSCC'93))
Category: Analog Circuits and Signal Processing
Keyword: 
PLLjittertime-domain simulationphase detectorNRZretiming
 Summary | Full Text:PDF(633.5KB)