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Keyword : MOS analog circuit

An Equivalent MOSFET Cell Using Adaptively Biased Source-Coupled Pair Hiroki SATO Akira HYOGO Keitaro SEKINE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/02/01 Vol. E86-A No. 2 pp. 357-363 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics) Category: Keyword: MOS analog circuit, threshold voltage, source-coupled pair, adaptively bias technique,
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A Phase Compensation Technique without Capacitors for the CMOS Circuit with a Very Low Impedance Terminal Eitake IBARAGI Akira HYOGO Keitaro SEKINE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2000/02/20 Vol. E83-A No. 2 pp. 236-242 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics) Category: Keyword: analog signal processing, MOS analog circuit, phase compensation, low impedance,
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A Very High Output Impedance Tail Current Source for Low Voltage Applications Eitake IBARAGI Akira HYOGO Keitaro SEKINE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2000/02/20 Vol. E83-A No. 2 pp. 204-209 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics) Category: Keyword: analog signal processing, MOS analog circuit, tail current source, high output impedance, low voltage operation,
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A CMOS Analog Multiplier Free from Mobility Reduction and Body Effect Eitake IBARAGI Akira HYOGO Keitaro SEKINE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1999/02/20 Vol. E82-A No. 2 pp. 327-334 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics) Category: Keyword: analog signal processing, MOS analog circuit, analog multiplier, mobility reduction, body effect,
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Design of a Sub-1. 5 V, 20 MHz, 0. 1% MOS Current-Mode Sample-and-Hold Circuit Yasuhiro SUGIMOTO Masahiro SEKIYA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1998/02/20 Vol. E81-A No. 2 pp. 258-260 Type of Manuscript: Special Section LETTER (Special Section on Analog Circuit Techniques in the Digital-Oriented Era) Category: Keyword: low voltage, high speed, high accuracy, MOS analog circuit, sample-and-hold circuit,
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A Low Power Dissipation Technique for a Low Voltage OTA Eitake IBARAGI Akira HYOGO Keitaro SEKINE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1998/02/20 Vol. E81-A No. 2 pp. 237-243 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques in the Digital-Oriented Era) Category: Keyword: analog signal processing, MOS analog circuit, MOS OTA, low voltage power supply, low power dissipation,
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A Study of the Signal-to-Noise Ratio of a High-Speed Current-Mode CMOS Sample-and-Hold Circuit Yasuhiro SUGIMOTO Masahiro SEKIYA Tetsuya IIDA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1997/10/20 Vol. E80-A No. 10 pp. 1986-1993 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: signal-to-noise ratio, noise analysis, sample-and-hold circuit, current-mode circuit, MOS analog circuit,
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1: n² MOS Cascode Circuits and Their Applications Koichi TANNO Okihiko ISHIZUKA Zheng TANG
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1996/12/20 Vol. E79-A No. 12 pp. 2159-2165 Type of Manuscript: PAPER Category: Analog Signal Processing Keyword: MOS analog circuit, MOS LSI, circuit theory and design, integrated circuit, threshold voltage,
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Design of a Novel MOS V_T Extractor Circuit Koichi TANNO Okihiko ISHIZUKA Zhen TANG
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1995/09/20 Vol. E78-C No. 9 pp. 1306-1310 Type of Manuscript: LETTER Category: Electronic Circuits Keyword: MOS analog circuit, threshold voltage, MOS LSI, circuit theory and design, integrated circuit,
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A Study of a MOS VCO Circuit by Using a Current–Controlled Differential Delay Cell Yasuhiro SUGIMOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1994/11/20 Vol. E77-A No. 11 pp. 1929-1931 Type of Manuscript: Special Section LETTER (Special Section of Letters Selected from the 1994 IEICE Spring Conference) Category: Keyword: MOS analog circuit, PLL, VCO, current control, differential delay cell,
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