IEICE SEARCH SYSTEM

Keyword : LSI

Impact of Floating Body Type DRAM with the Vertical MOSFET Yuto NORIFUSA Tetsuo ENDOH
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2011/05/01 Vol. E94-C No. 5 pp. 705-711 Type of Manuscript: Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices) Category: Keyword: floating body type DRAM, 1T-DRAM, memory architecture, vertical MOSFET, 3D structured device, LSI,
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Sub-10 nm Multi-Nano-Pillar Type Vertical MOSFET Tetsuo ENDOH Koji SAKUI Yukio YASUDA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2010/05/01 Vol. E93-C No. 5 pp. 557-562 Type of Manuscript: Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices) Category: Emerging Devices Keyword: vertical MOSFET, 3D structured device, MOSFET, LSI,
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A PVT Tolerant STM-16 Clock-and-Data Recovery LSI Using an On-Chip Loop-Gain Variation Compensation Architecture in 0.20-µm CMOS/SOI Yusuke OHTOMO Hiroshi KOIZUMI Kazuyoshi NISHIMURA Masafumi NOGAWA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2008/04/01 Vol. E91-C No. 4 pp. 655-661 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: LSI, CDR, CMOS, SOI, jitter,
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Bit-Serial Single Flux Quantum Microprocessor CORE Akira FUJIMAKI Masamitsu TANAKA Takahiro YAMADA Yuki YAMANASHI Heejoung PARK Nobuyuki YOSHIKAWA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2008/03/01 Vol. E91-C No. 3 pp. 342-349 Type of Manuscript: Special Section PAPER (Special Section on Recent Progress in Superconductive Digital Electronics) Category: INVITED Keyword: superconductor, microprocessor, single flux quantum, bit-serial, LSI,
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LSI On-Chip Optical Interconnection with Si Nano-Photonics Junichi FUJIKATA Kenichi NISHI Akiko GOMYO Jun USHIDA Tsutomu ISHI Hiroaki YUKAWA Daisuke OKAMOTO Masafumi NAKADA Takanori SHIMIZU Masao KINOSHITA Koichi NOSE Masayuki MIZUNO Tai TSUCHIZAWA Toshifumi WATANABE Koji YAMADA Seiichi ITABASHI Keishi OHASHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2008/02/01 Vol. E91-C No. 2 pp. 131-137 Type of Manuscript: Special Section PAPER (Special Section on Silicon Photonics Technologies and Their Applications) Category: INVITED Keyword: optical interconnect, LSI, Si nano-photonics, SiON waveguide, Si nano-photodiode, surface plasmon antenna, TIA-less optical clock circuit,
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The Front-End LSI with a 5-Tap PRML for 2 Reading and Writing of BD-R/RW/ROM GoangSeog CHOI JumHan BAE HyunSoo PARK
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/04/01 Vol. E90-C No. 4 pp. 727-730 Type of Manuscript: Special Section LETTER (Special Section on Low-Power, High-Speed LSIs and Related Technologies) Category: Digital Keyword: BD, LSI, PRML, OPC, Viterbi detector,
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Design of a Neural Network Chip for the Burst ID Model with Ability of Burst Firing Shinya SUENAGA Yoshihiro HAYAKAWA Koji NAKAJIMA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/04/01 Vol. E90-A No. 4 pp. 715-723 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: burst firing, neural network, optimization problem, LSI,
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Mixed Signal SoC Era Akira MATSUZAWA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2004/06/01 Vol. E87-C No. 6 pp. 867-877 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit and Device Technologies) Category: INVITED Keyword: CMOS, LSI, system LSI, mixed signal technology, analog circuit, LSI design, analog device,
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Cancellation of Multiple Echoes by Multiple Autonomic and Distributed Echo Canceler Units Akihiko SUGIYAMA Kenji ANZAI Hiroshi SATO Akihiro HIRANO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1998/11/20 Vol. E81-A No. 11 pp. 2361-2369 Type of Manuscript: PAPER Category: Digital Signal Processing Keyword: adaptive filter, echo, multiple echoes, echo canceler, sparse-tap, algorithm, LSI,
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Low Power Management Method for PDS ONU Logic LSIs Koichi SAITO Kiyoshi MATSUMOTO Kennosuke FUKAMI
Publication: IEICE TRANSACTIONS on Communications Publication Date: 1998/03/20 Vol. E81-B No. 3 pp. 604-608 Type of Manuscript: PAPER Category: Communication Device and Circuit Keyword: LSI, logic LSI, low power, PDS, ONU,
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A High-Performance Multicast Switch and Its Feasibility Study Shigeo URUSHIDANI Shigeki HINO Yusuke OHTOMO Sadayuki YASUDA
Publication: IEICE TRANSACTIONS on Communications Publication Date: 1998/02/20 Vol. E81-B No. 2 pp. 284-296 Type of Manuscript: Special Section PAPER (Special Issue on ATM Switching Systems for future B-ISDN) Category: Multicasting in ATM switch Keyword: ATM, switch, multicast, rerouting, banyan, LSI,
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A New Description of MOS Circuits at Switch-Level with Applications Massoud PEDRAM Xunwei WU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1997/10/20 Vol. E80-A No. 10 pp. 1892-1901 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: MOS, LSI, pass-transistor logic, switching theory, low power design,
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A Balanced-Mesh Clock Routing Technique for Performance Improvement Hidenori SATO Hiroaki MATSUDA Akira ONOZAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1997/08/20 Vol. E80-A No. 8 pp. 1489-1495 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: LSI, CAD, layout design, clock skew, partitioning, routing, MPEG2,
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A 3.2 GFLOPS Neural Network Accelerator Shinji KOMORI Yutaka ARIMA Yoshikazu KONDO Hirono TSUBOTA Ken-ichi TANAKA Kazuo KYUMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1997/07/20 Vol. E80-C No. 7 pp. 859-867 Type of Manuscript: INVITED PAPER (Special Issue on New Concept Device and Novel Architecture LSIs) Category: Keyword: neural network, parallel processing, SIMD, LSI,
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A Learning Algorithm for a Neural Network LSI with Restricted Integer Weights Tomohisa KIMURA Takeshi SHIMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1997/07/20 Vol. E80-C No. 7 pp. 983-989 Type of Manuscript: Special Section PAPER (Special Issue on New Concept Device and Novel Architecture LSIs) Category: Neural Networks and Chips Keyword: neural networks, learning, analog, LSI, accuracy,
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Hierarchical Fault Tracing for VLSIs with Bi-directional Busses from CAD Layout Data in the CAD-Linked EB Test System Katsuyoshi MIURA Koji NAKAMAE Hiromu FUJIOKA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1997/03/20 Vol. E80-C No. 3 pp. 498-502 Type of Manuscript: LETTER Category: Integrated Electronics Keyword: bi-directional bus, circuit extraction from CAD layout, electron beam testing, LSI,
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Low Power Design Technology for Digital LSIs Tadayoshi ENOMOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1996/12/20 Vol. E79-C No. 12 pp. 1639-1649 Type of Manuscript: INVITED PAPER (Special Issue on Low-Power LSI Technologies) Category: Keyword: power dissipation, active power dissipation, stand-by power dissipation, low power circuit technology, LSI, CMOS LSIs, GaAs LSIs, mlulti-media LSIs, video codec LSIs, signal handling capability, throughput, clock frequency, video signal processor, VSP, DSP. H.261, MPEG2,
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VLSI-Oriented Input and Output Buffered Switch Architecture for High-Speed ATM Backbone Nodes Yukio KAMATANI Yoshihiro OHBA Yoshimitsu SHIMOJO Koutarou ISE Masahiko MOTOYAMA Toshitada SAITO
Publication: IEICE TRANSACTIONS on Communications Publication Date: 1996/05/20 Vol. E79-B No. 5 pp. 647-657 Type of Manuscript: Special Section PAPER (Special Issue on High Speed Local Area Network) Category: Keyword: ATM, switch, node, high-speed, backbone, flow control, input buffer, output buffer, shared buffer, multicast, QoS, LSI,
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An Analytical Modeling of Three Primary Wiring Capacitance Components for Multi-Layer Interconnect Structure Susumu KUROSAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1995/12/20 Vol. E78-A No. 12 pp. 1793-1798 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: capacitance, modeling, interconnect, LSI, LPE,
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Overview of Low-Power ULSI Circuit Techniques Tadahiro KURODA Takayasu SAKURAI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1995/04/20 Vol. E78-C No. 4 pp. 334-344 Type of Manuscript: INVITED PAPER (Special Issue on Low-Voltage, Low-Power Integrated Circuits) Category: Keyword: LSI, CMOS, low-power, low-voltage, power-delay product, energy-delay product, pass-transistor logic,
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Synergistic Power/Area Optimization with Transistor Sizing and Wire Length Minimization Masaaki YAMADA Sachiko KUROSAWA Reiko NOJIMA Naohito KOJIMA Takashi MITSUHASHI Nobuyuki GOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1995/04/20 Vol. E78-C No. 4 pp. 441-446 Type of Manuscript: Special Section PAPER (Special Issue on Low-Voltage, Low-Power Integrated Circuits) Category: DA/Architecture Keyword: LSI, layout, transistor sizing, low power, CAD,
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A Global Router for Analog Function Blocks Based on the Branch-and-Bound Algorithm Tadanao TSUBOTA Masahiro KAWAKITA Takahiro WATANABE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1995/03/20 Vol. E78-A No. 3 pp. 345-352 Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 7th Karuizawa Workshop on Circuits and Systems) Category: VLSI Design Technology and CAD Keyword: branch-and-bound, layout, global routing, channel-intersection graph, analog, LSI, CAD,
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An Efficient Self-Timed Queue Architecture for ATM Switch LSIs Harufusa KONDOH Hideaki YAMANAKA Masahiko ISHIWAKI Yoshio MATSUDA Masao NAKAYA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1994/12/20 Vol. E77-C No. 12 pp. 1865-1872 Type of Manuscript: Special Section PAPER (Special Issue on Multimedia, Analog and Processing LSIs) Category: Multimedia System LSIs Keyword: ATM, ATM switch, LSI, self-timed systems,
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Development of Improved Low Power MUSE (HDTV) Decoder Chip Set 2.5th Generation MUSE Chip Set Kiyoshi KOHIYAMA Kota OTSUBO Hidenaga TAKAHASHI Kiyotaka OGAWA Yukio OTOBE
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1994/12/20 Vol. E77-C No. 12 pp. 1859-1864 Type of Manuscript: Special Section PAPER (Special Issue on Multimedia, Analog and Processing LSIs) Category: Multimedia System LSIs Keyword: HDTV, MUSE, LSI, power,
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Research Topics and Results on Analog Circuit Design for LSI Nobuo FUJII
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1993/07/20 Vol. E76-A No. 7 pp. 1061-1069 Type of Manuscript: Special Section PAPER (Special Section on Surveys of Researches in CAS Fields in the Last Two Decades, I) Category: Keyword: analog circuits, LSI,
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Polyacetylene for Soliton Devices Nobuo SASAKI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/07/20 Vol. E76-C No. 7 pp. 1056-1063 Type of Manuscript: INVITED PAPER (Special Issue on New Architecture LSIs) Category: Keyword: polyacetylene, soliton, LSI, one-dimensional conductor, molecular device,
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A Shared Multibuffer Architecture for High-Speed ATM Switch LSIs Harufusa KONDOH Hiromi NOTANI Hideaki YAMANAKA Keiichi HIGASHITANI Hirotaka SAITO Isamu HAYASHI Yoshio MATSUDA Kazuyoshi OSHIMA Masao NAKAYA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/07/20 Vol. E76-C No. 7 pp. 1094-1101 Type of Manuscript: Special Section PAPER (Special Issue on New Architecture LSIs) Category: Improved Binary Digital Architectures Keyword: B-ISDN, ATM, switch, LSI, BiCMOS,
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Precise Linewidth Measurement Using a Scanning Electron Probe Fumio MIZUNO Satoru YAMADA Akihiro MIURA Kenji TAKAMOTO Tadashi OHTAKA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/04/20 Vol. E76-C No. 4 pp. 600-606 Type of Manuscript: Special Section PAPER (Special Issue on Sub-Half Micron Si Device and Process Technologies) Category: Process Technology Keyword: LSI, metrology system, scanning electron probe, measurement accuracy, reproducibility, linearity, repeatability,
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High Speed Sub-Half Micron SATURN Transistor Using Epitaxial Base Technology Hirokazu FUJIMAKI Kenichi SUZUKI Yoshio UMEMURA Koji AKAHANE
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/04/20 Vol. E76-C No. 4 pp. 577-581 Type of Manuscript: Special Section PAPER (Special Issue on Sub-Half Micron Si Device and Process Technologies) Category: Device Technology Keyword: intergrated electronics, bipolar transistor, LSI, selective epitaxy, self-alignment, SIC,
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Integrated Circuits for Ultra-High-Speed Optical Fiber Transmission Systems Kohji HOHKAWA Shinji MATSUOKA Kazuo HAGIMOTO Kiyoshi NAKAGAWA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/01/20 Vol. E76-C No. 1 pp. 68-77 Type of Manuscript: INVITED PAPER (Special Issue on Opto-Electronics and LSI) Category: LSI Technology for Opto-Electronics Keyword: optical fiber, transmission system, LSI, GaAs, Si,
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An MOS Operational Transconductance Amplifier and an MOS Four-Quadrant Analog Multiplier Using the Quadritail Cell Katsuji KIMURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1992/12/20 Vol. E75-A No. 12 pp. 1774-1776 Type of Manuscript: Special Section LETTER (Special Section on the 1992 IEICE Fall Conference) Category: Keyword: OTA, multiplier, transconductance, quadritail cell, MOS, LSI,
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Isolation Characteristics in GaAs ICs on Semi-Insulating Substrate Kazuyuki INOKUCHI Yuko SEKINO-ITOH Yoshiaki SANO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1992/10/20 Vol. E75-C No. 10 pp. 1154-1164 Type of Manuscript: Special Section PAPER (Special Issue on Compound Semiconductor Integrated Circuits) Category: Keyword: isolation, leak, sidegate, M-i-n, LSI,
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