Keyword : LFSR


Reseeding-Oriented Test Power Reduction for Linear-Decompression-Based Test Compression Architectures
Tian CHEN Dandan SHEN Xin YI Huaguo LIANG Xiaoqing WEN Wei WANG 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2016/11/01
Vol. E99-D  No. 11 ; pp. 2672-2681
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
low power testdata compressionLFSRX-filling
 Summary | Full Text:PDF(2MB)

Design of q-Parallel LFSR-Based Syndrome Generator
Seung-Youl KIM Kyoung-Rok CHO Je-Hoon LEE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2015/07/01
Vol. E98-C  No. 7 ; pp. 594-596
Type of Manuscript:  BRIEF PAPER
Category: 
Keyword: 
error control codeparallel architectureLFSRBCH
 Summary | Full Text:PDF(450.4KB)

Security Analysis of a Variant of Self-Shrinking Generator
Dong Hoon LEE Je Hong PARK Jae Woo HAN 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/07/01
Vol. E91-A  No. 7 ; pp. 1824-1827
Type of Manuscript:  LETTER
Category: Cryptography and Information Security
Keyword: 
stream cipherLFSRself-shrinking generatorguess-and-determine attack
 Summary | Full Text:PDF(81.7KB)

Application of High Quality Built-in Test Using Neighborhood Pattern Generator to Industrial Designs
Kazumi HATAYAMA Michinobu NAKAO Yoshikazu KIYOSHIGE Koichiro NATSUME Yasuo SATO Takaharu NAGUMO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12 ; pp. 3318-3323
Type of Manuscript:  Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: Test
Keyword: 
BISTtest pattern generatorneighborhood patternLFSRreseeding
 Summary | Full Text:PDF(429.3KB)

Seed Selection Procedure for LFSR-Based Random Pattern Generators
Kenichi ICHINO Ko-ichi WATANABE Masayuki ARAI Satoshi FUKUMOTO Kazuhiko IWASAKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12 ; pp. 3063-3071
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Timing Verification and Test Generation
Keyword: 
BISTLFSRtest-per-clocktest-per-scanseedpolynomial
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A Built-in Reseeding Technique for LFSR-Based Test Pattern Generation
Youhua SHI Zhe ZHANG Shinji KIMURA Masao YANAGISAWA Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12 ; pp. 3056-3062
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Timing Verification and Test Generation
Keyword: 
reseedingLFSRBISTtest pattern generation
 Summary | Full Text:PDF(1MB)

Exact Expected Test Length Generated by LFSRs for Circuits Containing Hard Random-Pattern-Resistant Faults
Kazuhiko IWASAKI Hiroyuki GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/05/25
Vol. E81-A  No. 5 ; pp. 885-888
Type of Manuscript:  Special Section LETTER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
BISTtest lengthrandom-pattern-resistant faultLFSRinteger partition problem
 Summary | Full Text:PDF(236.5KB)