Keyword : LDPC decoder

An Area-Efficient Reconfigurable LDPC Decoder with Conflict Resolution
Changsheng ZHOU  Yuebin HUANG  Shuangqu HUANG  Yun CHEN  Xiaoyang ZENG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/04/01
Vol. E95-C  No. 4  pp. 478-486
Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
LDPC decoder,  TDMP,  CMMB,  DTMB,  conflict resolution, 
  Summary |  Full Text:PDF (1.8MB)
A 6.72-Gb/s 8 pJ/bit/iteration IEEE 802.15.3c LDPC Decoder Chip
Zhixiang CHEN  Xiao PENG  Xiongxin ZHAO  Leona OKAMURA  Dajiang ZHOU  Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/12/01
Vol. E94-A  No. 12  pp. 2587-2596
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
WPAN,  IEEE802.15.3c,  LDPC decoder,  high data rate,  power-efficient, 
  Summary |  Full Text:PDF (1.6MB)
A Fast Systematic Optimized Comparison Algorithm for CNU Design of LDPC Decoders
Jui-Hui HUNG  Sau-Gee CHEN 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/11/01
Vol. E94-A  No. 11  pp. 2246-2253
Type of Manuscript: Special Section PAPER (Special Section on Smart Multimedia & Communication Systems)
Category: Communication Theory and Signals
Keyword: 
channel coding,  LDPC decoder,  comparison operation,  algorithm,  hardware, 
  Summary |  Full Text:PDF (768.3KB)
Generic Permutation Network for QC-LDPC Decoder
Xiao PENG  Xiongxin ZHAO  Zhixiang CHEN  Fumiaki MAEHARA  Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/12/01
Vol. E93-A  No. 12  pp. 2551-2559
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
LDPC decoder,  reconfigurable,  permutation network,  parallelism, 
  Summary |  Full Text:PDF (1.2MB)
Permutation Network for Reconfigurable LDPC Decoder Based on Banyan Network
Xiao PENG  Zhixiang CHEN  Xiongxin ZHAO  Fumiaki MAEHARA  Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/03/01
Vol. E93-C  No. 3  pp. 270-278
Type of Manuscript: Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration)
Category: 
Keyword: 
permutation,  banyan network,  LDPC decoder,  reconfigurable, 
  Summary |  Full Text:PDF (705KB)