Keyword : L1/L2


A Two-Level Cache Design Space Exploration System for Embedded Applications
Nobuaki TOJO Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Vol. E92-A  No. 12 ; pp. 3238-3247
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Embedded, Real-Time and Reconfigurable Systems
Keyword: 
two-level cacheL1/L2cache optimizationdesign space explorationcache simulationembedded system
 Summary | Full Text:PDF(522.3KB)

CMOS Front-End Circuits of Dual-Band GPS Receiver
Yoshihiro UTSUROGI Masaki HARUOKA Toshimasa MATSUOKA Kenji TANIGUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/06/01
Vol. E88-C  No. 6 ; pp. 1275-1279
Type of Manuscript:  Special Section LETTER (Special Section on Analog Circuit and Device Technologies)
Category: RF
Keyword: 
dual-band GPS receiverL1/L2LNAimage-reject mixerimage-rejection ratio (IMRR)
 Summary | Full Text:PDF(691.4KB)