Keyword : IDDQ testing


IDDQ Outlier Screening through Two-Phase Approach: Clustering-Based Filtering and Estimation-Based Current-Threshold Determination
Michihiro SHINTANI Takashi SATO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2014/08/01
Vol. E97-D  No. 8 ; pp. 2095-2104
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
IDDQ testingk-means clusteringstatistical leakage current analysisBayes' theoremsimulated annealing
 Summary | Full Text:PDF(1.2MB)

Device-Parameter Estimation through IDDQ Signatures
Michihiro SHINTANI Takashi SATO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/02/01
Vol. E96-D  No. 2 ; pp. 303-313
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
IDDQ testingstatistical leakage current analysisBayes' theorem
 Summary | Full Text:PDF(1.3MB)

A CMOS Built-In Current Sensor for IDDQ Testing
Jeong Beom KIM Seung Ho HONG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/06/01
Vol. E89-C  No. 6 ; pp. 868-870
Type of Manuscript:  LETTER
Category: Integrated Electronics
Keyword: 
IDDQ testingcurrent testingBICSreliability
 Summary | Full Text:PDF(470.6KB)

Test Sequence Generation for Test Time Reduction of IDDQ Testing
Hiroyuki YOTSUYANAGI Masaki HASHIZUME Takeomi TAMESADA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2004/03/01
Vol. E87-D  No. 3 ; pp. 537-543
Type of Manuscript:  Special Section PAPER (Special Section on Test and Verification of VLSI)
Category: Test Generation and Compaction
Keyword: 
IDDQ testingbridging faultsswitching currentsupply current testCMOS circuits
 Summary | Full Text:PDF(1MB)

An IDDQ Sensor Driven by Abnormal IDDQ
Yukiya MIURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2000/10/25
Vol. E83-D  No. 10 ; pp. 1860-1867
Type of Manuscript:  PAPER
Category: Fault Tolerance
Keyword: 
built-in testingCMOS circuitsIDDQ sensor circuitsIDDQ testinglow-voltage ICs
 Summary | Full Text:PDF(3.7MB)

An Analysis of the Relationship between IDDQ Testability and D-Type Flip-Flop Structure
Yukiya MIURA Hiroshi YAMAZAKI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/10/25
Vol. E81-D  No. 10 ; pp. 1072-1078
Type of Manuscript:  PAPER
Category: Fault Tolerant Computing
Keyword: 
IDDQ testingbridging faultsflip-flopsfault analysis
 Summary | Full Text:PDF(571.6KB)

An Iterative Improvement Method for Generating Compact Tests for IDDQ Testing of Bridging Faults
Tsuyoshi SHINOGI Terumine HAYASHI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/07/25
Vol. E81-D  No. 7 ; pp. 682-688
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Diagnosis of VLSI)
Category: IDDQ Testing
Keyword: 
compactionIDDQ testingiterative improvement methodbridging faultATPG
 Summary | Full Text:PDF(651.4KB)

Test Generation for Sequential Circuits under IDDQ Testing
Toshiyuki MAEDA Yoshinobu HIGAMI Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/07/25
Vol. E81-D  No. 7 ; pp. 689-696
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Diagnosis of VLSI)
Category: IDDQ Testing
Keyword: 
sequential circuittest generationIDDQ testingbridging fault
 Summary | Full Text:PDF(707.5KB)