Keyword : FPGAs


A Fast MER Enumeration Algorithm for Online Task Placement on Reconfigurable FPGAs
Tieyuan PAN Lian ZENG Yasuhiro TAKASHIMA Takahiro WATANABE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/12/01
Vol. E99-A  No. 12 ; pp. 2412-2424
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
fast MER enumerationFPGAslow memory consumption
 Summary | Full Text:PDF(1.7MB)

High-Speed Fully-Adaptable CRC Accelerators
Amila AKAGIC Hideharu AMANO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/06/01
Vol. E96-D  No. 6 ; pp. 1299-1308
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
reconfigurable computingFPGAscyclic redundancy checksadaptabilityaccelerators
 Summary | Full Text:PDF(1.2MB)

A Domain Partition Model Approach to the Online Fault Recovery of FPGA-Based Reconfigurable Systems
Lihong SHANG Mi ZHOU Yu HU Erfu YANG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/01/01
Vol. E94-A  No. 1 ; pp. 290-299
Type of Manuscript:  PAPER
Category: Nonlinear Problems
Keyword: 
fault-recoveryFPGAsreconfigurable systemsdomain partitionfault-tolerance
 Summary | Full Text:PDF(2.6MB)

Evaluation of a Field-Programmable VLSI Based on an Asynchronous Bit-Serial Architecture
Masanori HARIYAMA Shota ISHIHARA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/09/01
Vol. E91-C  No. 9 ; pp. 1419-1426
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Processors Based on Novel Concepts in Computation)
Category: 
Keyword: 
FPGAsreconfigurable VLSIsasynchronous architectureLEDR (Level-Encoded Dual-Rail) encoding
 Summary | Full Text:PDF(668.6KB)

Design of a Field-Programmable Digital Filter Chip Using Multiple-Valued Current-Mode Logic
Katsuhiko DEGAWA Takafumi AOKI Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/08/01
Vol. E86-A  No. 8 ; pp. 2001-2010
Type of Manuscript:  Special Section PAPER (Special Section on Digital Signal Processing)
Category: 
Keyword: 
multiple-valued logicsignal processorFPGAsFIR filters
 Summary | Full Text:PDF(2.9MB)

Accelerating the CKY Parsing Using FPGAs
Jacir L. BORDIM Yasuaki ITO Koji NAKANO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2003/05/01
Vol. E86-D  No. 5 ; pp. 803-810
Type of Manuscript:  Special Section PAPER (Special Issue on Reconfigurable Computing)
Category: 
Keyword: 
CKY parsingFPGAsreconfigurable architecturesreconfigurable computing
 Summary | Full Text:PDF(850.3KB)

A Technique for Modelling Dynamic Reconfiguration with Improved Simulation Accuracy
Milan VASILKO David CABANIS 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/11/25
Vol. E82-A  No. 11 ; pp. 2465-2474
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
logic simulationDynamically Reconfigurable Logicrun-time reconfigurationVHDLFPGAs
 Summary | Full Text:PDF(1.1MB)

Signed-Weight Arithmetic and Its Application to a Field-Programmable Digital Filter Architecture
Takafumi AOKI Yoshiki SAWADA Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/09/25
Vol. E82-C  No. 9 ; pp. 1687-1698
Type of Manuscript:  Special Section PAPER (Special Issue on Integrated Electronics and New System Paradigms)
Category: Configurable Computing and Fault Tolerance
Keyword: 
computer arithmeticredundant number systemsdigital signal processingFIR filterFPGAs
 Summary | Full Text:PDF(2.7MB)

Reduction of the Number of FPGA Blocks by Maximizing Flexibility of Internal Functions
Takenori KOUDA Shigeru YAMASHITA Yahiko KAMBAYASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/12/25
Vol. E81-A  No. 12 ; pp. 2554-2562
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
logic optimizationFPGAsSPFDsPSPFDs
 Summary | Full Text:PDF(818.2KB)

Plastic Cell Architecture: A Scalable Device Architecture for General-Purpose Reconfigurable Computing
Kouichi NAGAMI Kiyoshi OGURI Tsunemichi SHIOZAWA Hideyuki ITO Ryusuke KONISHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/09/25
Vol. E81-C  No. 9 ; pp. 1431-1437
Type of Manuscript:  Special Section PAPER (Special Issue on Novel VLSI Processor Architectures)
Category: 
Keyword: 
reconfigurable computingFPGAsobject-orientedhardware description languagecellular automata
 Summary | Full Text:PDF(687.8KB)