IEICE SEARCH SYSTEM

Keyword : FPGA

Adaptive Analog-to-Information Converter Design with Limited Random Sequence Modulation Chao ZHANG Jialuo XIAO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2013/02/01 Vol. E96-A No. 2 pp. 469-476 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics) Category: Keyword: adaptive AIC, analog-to-information converter, limited random sequence, prototype system, FPGA,
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Design and Implementation of a Handshake Join Architecture on FPGA Yasin OGE Takefumi MIYOSHI Hideyuki KAWASHIMA Tsutomu YOSHINAGA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2012/12/01 Vol. E95-D No. 12 pp. 2919-2927 Type of Manuscript: Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking) Category: Computer Architecture Keyword: FPGA, data stream processing, window join operator, accelerator, handshake join,
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FPGA Design of User Monitoring System for Display Power Control Tomoaki ANDO Vasily G. MOSHNYAGA Koji HASHIMOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2012/12/01 Vol. E95-A No. 12 pp. 2364-2372 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High-Level Synthesis and System-Level Design Keyword: seven-segment rectangular template, between the eyes region, eye-detection, user monitoring, FPGA, display, power management,
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Fault-Injection Analysis to Estimate SEU Failure in Time by Using Frame-Based Partial Reconfiguration Yoshihiro ICHINOMIYA Tsuyoshi KIMURA Motoki AMAGASAKI Morihiro KUGA Masahiro IIDA Toshinori SUEYOSHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2012/12/01 Vol. E95-A No. 12 pp. 2347-2356 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High-Level Synthesis and System-Level Design Keyword: FPGA, partial reconfiguration, fault-injection analysis, soft-error, dependability,
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Region Oriented Routing FPGA Architecture for Dynamic Power Gating Ce LI Yiping DONG Takahiro WATANABE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2012/12/01 Vol. E95-A No. 12 pp. 2199-2207 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Physical Level Design Keyword: FPGA, low power, switch box, routing,
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An Improved Look-Up Table-Based FPGA Implementation of Image Warping for CMOS Image Sensors Se-yong RO Lin-bo LUO Jong-wha CHONG
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2012/11/01 Vol. E95-D No. 11 pp. 2682-2692 Type of Manuscript: PAPER Category: Image Processing and Video Processing Keyword: Image warping, look-up table, perspective transformation, panorama unrolling, FPGA,
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An FPGA-Based Information Detection Hardware System Employing Multi-Match Content Addressable Memory Duc-Hung LE Katsumi INOUE Masahiro SOWA Cong-Kha PHAM
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2012/10/01 Vol. E95-A No. 10 pp. 1708-1717 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: FPGA, information detection, content addressable memory, random access memory, parallel operation, multi-match,
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Finite Virtual State Machines Raouf SENHADJI-NAVARRO Ignacio GARCIA-VARGAS
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2012/10/01 Vol. E95-D No. 10 pp. 2544-2547 Type of Manuscript: LETTER Category: Computer System Keyword: finite state machine, reconfiguration, RAM, FPGA,
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Performance Improvement and Congestion Reduction of Large FPGAs Using On-Chip Microwave Interconnects Mohammad Taghi TEIMOORI Ali JAHANIAN Adel DOKHANCHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2012/10/01 Vol. E95-C No. 10 pp. 1610-1619 Type of Manuscript: Special Section PAPER (Special Section on Recent Progress in Microwave and Millimeter-Wave Technologies) Category: Keyword: microwave on-chip interconnect, FPGA, performance,
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Neuron-Like Responses and Bifurcations of a Generalized Asynchronous Sequential Logic Spiking Neuron Model Takashi MATSUBARA Hiroyuki TORIKAI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2012/08/01 Vol. E95-A No. 8 pp. 1317-1328 Type of Manuscript: PAPER Category: Nonlinear Problems Keyword: neuron model, nonlinear dynamics, bifurcation phenomena, asynchronous sequential logic circuit, asynchronous cellular automaton, FPGA,
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A Dynamically Reconfigurable FPGA-Based Pattern Matching Hardware for Subclasses of Regular Expressions Yusaku KANETA Shingo YOSHIZAWA Shin-ichi MINATO Hiroki ARIMURA Yoshikazu MIYANAGA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2012/07/01 Vol. E95-D No. 7 pp. 1847-1857 Type of Manuscript: PAPER Category: Computer System Keyword: FPGA, string matching, regular expression matching, bit-parallel algorithm, event stream processing,
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Development of a Microwave Exciter for ⁸⁷Sr⁺ Ion Frequency Standards Iku HIRANO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2012/07/01 Vol. E95-C No. 7 pp. 1231-1233 Type of Manuscript: BRIEF PAPER Category: Keyword: highly stable microwave exciter, frequency stability, analog lead-lag filter, FPGA,
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Efficient LUT-Based Truncated Multiplier and Its Application in RGB to YCbCr Color Space Conversion Van-Phuc HOANG Cong-Kha PHAM
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2012/06/01 Vol. E95-A No. 6 pp. 999-1006 Type of Manuscript: PAPER Category: Digital Signal Processing Keyword: LUT-based computation, truncated multiplier, FPGA, color space conversion,
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Design and Implementation of the Parameterized Multi-Standard High-Throughput Radix-4 Viterbi Decoder on FPGA Rongchun LI Yong DOU Yuanwu LEI Shice NI Song GUO
Publication: IEICE TRANSACTIONS on Communications Publication Date: 2012/05/01 Vol. E95-B No. 5 pp. 1602-1611 Type of Manuscript: PAPER Category: Fundamental Theories for Communications Keyword: multi-standard, radix-4, Viterbi decoder, FPGA,
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Asynchronous Circuit Design on Field Programmable Gate Array Devices Jung-Lin YANG Shin-Nung LU Pei-Hsuan YU
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2012/04/01 Vol. E95-C No. 4 pp. 516-522 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology) Category: Keyword: asynchronous, bundled-data, burst-mode, extended burst-mode, FPGA, generalized C-element, HDL, self-timed,
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Energy Minimum Operation with Self Synchronous Gate-Level Autonomous Power Gating and Voltage Scaling Benjamin DEVLIN Makoto IKEDA Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2012/04/01 Vol. E95-C No. 4 pp. 546-554 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology) Category: Keyword: power gating, gate-level, pipeline, self synchronous, energy minimum operation, FPGA,
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A Design Method of a Regular Expression Matching Circuit Based on Decomposed Automaton Hiroki NAKAHARA Tsutomu SASAO Munehiro MATSUURA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2012/02/01 Vol. E95-D No. 2 pp. 364-373 Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems) Category: Design Methodology Keyword: regular expression, NFA, DFA, MNFAU, FPGA,
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FPGA Implementation of Metastability-Based True Random Number Generator Hisashi HATA Shuichi ICHIKAWA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2012/02/01 Vol. E95-D No. 2 pp. 426-436 Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems) Category: Application Keyword: TRNG, synchronous digital circuit, FPGA, entropy,
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A Physical Design Method for a New Memory-Based Reconfigurable Architecture without Switch Blocks Masatoshi NAKAMURA Masato INAGI Kazuya TANIGAWA Tetsuo HIRONAKA Masayuki SATO Takashi ISHIGURO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2012/02/01 Vol. E95-D No. 2 pp. 324-334 Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems) Category: Design Methodology Keyword: reconfigurable device, physical design, placement, routing, MPLD, FPGA, EDA,
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Region-Oriented Placement Algorithm for Coarse-Grained Power-Gating FPGA Architecture Ce LI Yiping DONG Takahiro WATANABE
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2012/02/01 Vol. E95-D No. 2 pp. 314-323 Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems) Category: Design Methodology Keyword: FPGA, low power, region, hierarchical design, power consumption,
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Hierarchical MFMO Circuit Modules for an Energy-Efficient SDR DBF Jeich MAR Chi-Cheng KUO Shin-Ru WU You-Rong LIN
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2012/02/01 Vol. E95-D No. 2 pp. 413-425 Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems) Category: Application Keyword: FPGA, MFMO, SDR, CR, ESPRIT, CORDIC,
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Efficient Sequential Architecture of AES CCM for the IEEE 802.16e Jae Deok JI Seok Won JUNG Jongin LIM
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2012/01/01 Vol. E95-D No. 1 pp. 185-187 Type of Manuscript: Special Section LETTER (Special Section on Trust, Security and Privacy in Computing and Communication Systems) Category: Privacy Keyword: cryptography, communication system security, integrated chip design, FPGA,
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Multi-Operand Adder Synthesis Targeting FPGAs Taeko MATSUNAGA Shinji KIMURA Yusuke MATSUNAGA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/12/01 Vol. E94-A No. 12 pp. 2579-2586 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis, Test and Verification Keyword: multi-operand adder, generalized parallel counter, arithmetic synthesis, FPGA,
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Low Power Placement and Routing for the Coarse-Grained Power Gating FPGA Architecture Ce LI Yiping DONG Takahiro WATANABE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/12/01 Vol. E94-A No. 12 pp. 2519-2527 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Physical Level Design Keyword: FPGA, low power, power domain, power consumption,
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Compact Architecture for ASIC and FPGA Implementation of the KASUMI Block Cipher Dai YAMAMOTO Kouichi ITOH Jun YAJIMA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/12/01 Vol. E94-A No. 12 pp. 2628-2638 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High-Level Synthesis and System-Level Design Keyword: block cipher, KASUMI, hardware, ASIC, FPGA, compact implementation,
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A Graph Rewriting Approach for Converting Asynchronous ROMs into Synchronous Ones Md. Nazrul Islam MONDAL Koji NAKANO Yasuaki ITO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2011/12/01 Vol. E94-D No. 12 pp. 2378-2388 Type of Manuscript: Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking) Category: Keyword: FPGA, block RAMs, asynchronous read operations, rewriting algorithm,
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Development and Outdoor Evaluation of an Experimental Platform in an 80-MHz Bandwidth 22 MIMO-OFDM System in 5.2-GHz Band Hisayoshi KANO Shingo YOSHIZAWA Takashi GUNJI Shougo OKAMOTO Morio TAWARAYAMA Yoshikazu MIYANAGA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2011/12/01 Vol. E94-D No. 12 pp. 2400-2408 Type of Manuscript: PAPER Category: Computer System Keyword: IEEE802.11ac, wideband MIMO-OFDM, FPGA, field experiment,
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FPGA-Specific Custom VLIW Architecture for Arbitrary Precision Floating-Point Arithmetic Yuanwu LEI Yong DOU Jie ZHOU
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2011/11/01 Vol. E94-D No. 11 pp. 2173-2183 Type of Manuscript: PAPER Category: Computer System Keyword: variable-precision floating-point (VP) arithmetic, Very Long Instruction Word (VLIW), elementary function, Newton's method, polynomial approximation, FPGA,
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3D-DCT Processor and Its FPGA Implementation Yuki IKEGAKI Toshiaki MIYAZAKI Stanislav G. SEDUKHIN
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2011/07/01 Vol. E94-D No. 7 pp. 1409-1418 Type of Manuscript: PAPER Category: Computer System Keyword: 3D-DCT, array processors, data manipulation, FPGA,
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ROM-Less Phase to Amplitude Converter Using Sine Wave Approximation Based on Harmonic Removal from Trapezoid Wave Hiroomi HIKAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/07/01 Vol. E94-A No. 7 pp. 1581-1584 Type of Manuscript: LETTER Category: Cryptography and Information Security Keyword: direct digital frequency synthesizer, phase to amplitude converter, sine approximation, FPGA,
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A Proposition of 600 Mbps WLAN-Like System with Low-Complexity MIMO Decoder for FPGA Implementation Wahyul Amien SYAFEI Yuhei NAGAO Ryuta IMASHIOYA Masayuki KUROSAKI Baiko SAI Hiroshi OCHI
Publication: IEICE TRANSACTIONS on Communications Publication Date: 2011/02/01 Vol. E94-B No. 2 pp. 491-498 Type of Manuscript: PAPER Category: Wireless Communication Technologies Keyword: FPGA, GLST, high throughput, MIMO, RTL design, WLAN,
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How to Maximize the Potential of FPGA-Based DSPs for Modular Exponentiation Daisuke SUZUKI Tsutomu MATSUMOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/01/01 Vol. E94-A No. 1 pp. 211-222 Type of Manuscript: Special Section PAPER (Special Section on Cryptography and Information Security) Category: Implementation Keyword: hardware architecture, modular exponentiation, Montgomery multiplication, FPGA, DSP,
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A VGA 30 fps Affine Motion Model Estimation VLSI for Real-Time Video Segmentation Yoshiki YUNBE Masayuki MIYAMA Yoshio MATSUDA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2010/12/01 Vol. E93-D No. 12 pp. 3284-3293 Type of Manuscript: PAPER Category: Computer System Keyword: affine motion model, motion estimation, video segmentation, real-time processing, VLSI, FPGA,
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Accelerating Boolean Matching Using Bloom Filter Chun ZHANG Yu HU Lingli WANG Lei HE Jiarong TONG
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2010/10/01 Vol. E93-A No. 10 pp. 1775-1781 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: FPGA, Boolean matching, Bloom filter, SAT, re-synthesis,
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A High Throughput Medium Access Control Implementation Based on IEEE 802.11e Standard Min Li HUANG Jin LEE Hendra SETIAWAN Hiroshi OCHI Sin-Chong PARK
Publication: IEICE TRANSACTIONS on Communications Publication Date: 2010/04/01 Vol. E93-B No. 4 pp. 948-960 Type of Manuscript: PAPER Category: Terrestrial Radio Communications Keyword: IEEE 802.11e, MAC, EDCA, FPGA,
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A Fast and Memory Efficient SPIHT Image Encoder Zhong-Ho CHEN Alvin W. Y. SU
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2010/03/01 Vol. E93-D No. 3 pp. 602-610 Type of Manuscript: PAPER Category: Image Processing and Video Processing Keyword: image coding, wavelet, set-partition in hierarchical trees (SPIHT), FPGA,
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Mapping Parallel FFT Algorithm onto SmartCell Coarse-Grained Reconfigurable Architecture Cao LIANG Xinming HUANG
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2010/03/01 Vol. E93-C No. 3 pp. 407-415 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: coarse-grained reconfigurable architecture, parallel FFT, energy efficiency, ASIC, FPGA, DSP,
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High-Speed Passphrase Search System for PGP Koichi SHIMIZU Daisuke SUZUKI Toyohiro TSURUMARU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2010/01/01 Vol. E93-A No. 1 pp. 202-209 Type of Manuscript: Special Section PAPER (Special Section on Cryptography and Information Security) Category: Application Keyword: passphrase, search, FPGA, PGP, security,
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Efficient Cut Enumeration Heuristics for Depth-Optimum Technology Mapping for LUT-Based FPGAs Taiga TAKATA Yusuke MATSUNAGA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/12/01 Vol. E92-A No. 12 pp. 3268-3275 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Embedded, Real-Time and Reconfigurable Systems Keyword: FPGA, technology mapping, cut enumeration,
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Pipelining a Multi-Mode SHA-384/512 Core with High Area Performance Rate Anh-Tuan HOANG Katsuhiro YAMAZAKI Shigeru OYANAGI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2009/10/01 Vol. E92-D No. 10 pp. 2034-2042 Type of Manuscript: PAPER Category: VLSI Systems Keyword: cryptography, SHA-2, fine-grained pipelining, FPGA,
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PAMELA: Pattern Matching Engine with Limited-Time Update for NIDS/NIPS Tran Ngoc THINH Surin KITTITORNKUN Shigenori TOMIYAMA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2009/05/01 Vol. E92-D No. 5 pp. 1049-1061 Type of Manuscript: PAPER Category: VLSI Systems Keyword: Cuckoo Hashing, dynamic update, pattern matching, FPGA, NIDS/NIPS,
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Application-Dependent Interconnect Testing of Xilinx FPGAs Based on Line Branches Partitioning Teng LIN Jianhua FENG Dunshan YU
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2009/05/01 Vol. E92-D No. 5 pp. 1197-1199 Type of Manuscript: LETTER Category: Dependable Computing Keyword: FPGA, application-dependent testing, line branch, Test Configuration,
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FPGA Implementation of Highly Modular Fast Universal Discrete Transforms Panan POTIPANTONG Phaophak SIRISUK Soontorn ORAINTARA Apisak WORAPISHET
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2009/04/01 Vol. E92-C No. 4 pp. 576-586 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: UDFHT, DHT, DST, DFT, DCT, FFT, FPGA, reconfigurable computing,
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A Link Removal Methodology for Application-Specific Networks-on-Chip on FPGAs Daihan WANG Hiroki MATSUTANI Michihiro KOIBUCHI Hideharu AMANO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2009/04/01 Vol. E92-D No. 4 pp. 575-583 Type of Manuscript: PAPER Category: VLSI Systems Keyword: network-on-chip, FPGA, customize, router,
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Autonomous Repair Fault Tolerant Dynamic Reconfigurable Device Kentaro NAKAHARA Shin'ichi KOUYAMA Tomonori IZUMI Hiroyuki OCHI Yukihiro NAKAMURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/12/01 Vol. E91-A No. 12 pp. 3612-3621 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Embedded, Real-Time and Reconfigurable Systems Keyword: fault tolerance, dependable, FPGA, reconfigurable device, soft error,
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Adaptive Impedance Matching System Using FPGA Processor for Efficient Control Algorithm Hirokazu OBA Minseok KIM Ryotaro TAMAKI Hiroyuki ARAI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2008/08/01 Vol. E91-C No. 8 pp. 1348-1355 Type of Manuscript: PAPER Category: Microwaves, Millimeter-Waves Keyword: antenna input impedance, automatic matching system, FPGA,
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Hardware Neural Network for a Visual Inspection System Seungwoo CHUN Yoshihiro HAYAKAWA Koji NAKAJIMA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/04/01 Vol. E91-A No. 4 pp. 935-942 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 20th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: hardware, visual inspection system, back-propagation, PCI-BUS, FPGA,
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Resource and Performance Evaluations of Fixed Point QRD-RLS Systolic Array through FPGA Implementation Yoshiaki YOKOYAMA Minseok KIM Hiroyuki ARAI
Publication: IEICE TRANSACTIONS on Communications Publication Date: 2008/04/01 Vol. E91-B No. 4 pp. 1068-1075 Type of Manuscript: PAPER Category: Wireless Communication Technologies Keyword: systolic array, QR decomposition, RLS, CORDIC, FPGA,
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A Design of the Signal Processing Hardware Platform for Communication Systems Byung Wook LEE Sung Ho CHO
Publication: IEICE TRANSACTIONS on Communications Publication Date: 2008/03/01 Vol. E91-B No. 3 pp. 939-942 Type of Manuscript: LETTER Category: Wireless Communication Technologies Keyword: OFDM, IEEE 802.16, FPGA, DSP, platform,
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Implementation of Joint Pre-FFT Adaptive Array Antenna and Post-FFT Space Diversity Combining for Mobile ISDB-T Receiver Dang Hai PHAM Jing GAO Takanobu TABATA Hirokazu ASATO Satoshi HORI Tomohisha WADA
Publication: IEICE TRANSACTIONS on Communications Publication Date: 2008/01/01 Vol. E91-B No. 1 pp. 127-138 Type of Manuscript: Special Section PAPER (Special Section on Cognitive Radio and Spectrum Sharing Technology) Category: Enabling Technology Keyword: adaptive array antenna, space diversity combining, OFDM, ISDB-T, FPGA, DSP,
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Diversification of Processors Based on Redundancy in Instruction Set Shuichi ICHIKAWA Takashi SAWADA Hisashi HATA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/01/01 Vol. E91-A No. 1 pp. 211-220 Type of Manuscript: Special Section PAPER (Special Section on Cryptography and Information Security) Category: Implementation Keyword: FPGA, embedded systems, instruction set, randomization, secure processor,
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A Port Combination Methodology for Application-Specific Networks-on-Chip on FPGAs Daihan WANG Hiroki MATSUTANI Michihiro KOIBUCHI Hideharu AMANO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2007/12/01 Vol. E90-D No. 12 pp. 1914-1922 Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems) Category: Reconfigurable System and Applications Keyword: Networks-on-Chip, FPGA, router, port combination,
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A Self-Reconfigurable Adaptive FIR Filter System on Partial Reconfiguration Platform Chang-Seok CHOI Hanho LEE
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2007/12/01 Vol. E90-D No. 12 pp. 1932-1938 Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems) Category: Reconfigurable System and Applications Keyword: partial reconfiguration, self-reconfiguration, adaptive FIR filter, FPGA,
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Multiple Sequence Alignment Based on Dynamic Programming Using FPGA Shingo MASUNO Tsutomu MARUYAMA Yoshiki YAMAGUCHI Akihiko KONAGAYA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2007/12/01 Vol. E90-D No. 12 pp. 1939-1946 Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems) Category: Reconfigurable System and Applications Keyword: multiple sequence alignment, dynamic programming, FPGA, reconfiguration,
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Optimization of the Body Bias Voltage Set (BBVS) for Flex Power FPGA Takashi KAWANAMI Masakazu HIOKI Yohei MATSUMOTO Toshiyuki TSUTSUMI Tadashi NAKAGAWA Toshihiro SEKIGAWA Hanpei KOIKE
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2007/12/01 Vol. E90-D No. 12 pp. 1947-1955 Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems) Category: Reconfigurable Device and Design Tools Keyword: FPGA, low-power, threshold voltage control, body bias,
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FPGA-Based Intrusion Detection System for 10 Gigabit Ethernet Toshihiro KATASHITA Yoshinori YAMAGUCHI Atusi MAEDA Kenji TODA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2007/12/01 Vol. E90-D No. 12 pp. 1923-1931 Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems) Category: Reconfigurable System and Applications Keyword: intrusion detection system, intrusion protection system, exact string matching, FPGA, 10 Gigabit Ethernet,
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Basic Characteristics and Learning Potential of a Digital Spiking Neuron Hiroyuki TORIKAI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/10/01 Vol. E90-A No. 10 pp. 2093-2100 Type of Manuscript: Special Section PAPER (Special Section on Nonlinear Theory and its Applications) Category: Neuron and Neural Networks Keyword: spiking neuron, digital dynamical system, learning, UWB, FPGA,
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Wide View Imaging System Using Eight Random Access Image Sensors Kenji IDE Ryusuke KAWAHARA Satoshi SHIMIZU Takayuki HAMAMOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/10/01 Vol. E90-C No. 10 pp. 1884-1891 Type of Manuscript: Special Section PAPER (Special Section on VLSI Technology toward Frontiers of New Market) Category: Image Sensor/Vision Chip Keyword: smart image sensor, wide view imaging, object tracking, FPGA, background subtraction,
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A 90 nm 4848 LUT-Based FPGA Enhancing Speed and Yield Utilizing Within-Die Delay Variations Kazutoshi KOBAYASHI Kazuya KATSUKI Manabu KOTANI Yuuri SUGIHARA Yohei KUME Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/10/01 Vol. E90-C No. 10 pp. 1919-1926 Type of Manuscript: Special Section PAPER (Special Section on VLSI Technology toward Frontiers of New Market) Category: Low-Power and High-Performance VLSI Circuit Technology Keyword: variation-aware, reconfigurable device, FPGA, yield, DFM,
	Summary \| Full Text:PDF (690.4KB)

Efficient Motion Estimation for H.264 Codec by Using Effective Scan Ordering Jeongae PARK Misun YOON Hyunchul SHIN
Publication: IEICE TRANSACTIONS on Communications Publication Date: 2007/07/01 Vol. E90-B No. 7 pp. 1839-1843 Type of Manuscript: LETTER Category: Devices/Circuits for Communications Keyword: motion estimation, absolute difference, H.264, FPGA,
	Summary \| Full Text:PDF (1MB)

Design Methods of Radix Converters Using Arithmetic Decompositions Yukihiro IGUCHI Tsutomu SASAO Munehiro MATSUURA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2007/06/01 Vol. E90-D No. 6 pp. 905-914 Type of Manuscript: PAPER Category: Computer Components Keyword: radix converter, LUT cascades, FPGA, functional decomposition,
	Summary \| Full Text:PDF (458.3KB)

A Performance-Driven Circuit Bipartitioning Method Considering Time-Multiplexed I/Os Masato INAGI Yasuhiro TAKASHIMA Yuichi NAKAMURA Yoji KAJITANI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/05/01 Vol. E90-A No. 5 pp. 924-931 Type of Manuscript: Special Section PAPER (Special Section on Discrete Mathematics and Its Applications) Category: Keyword: circuit partitioning, time-multiplexed I/O, FPGA, pin constraint,
	Summary \| Full Text:PDF (402.5KB)

A 90 nm LUT Array for Speed and Yield Enhancement by Utilizing Within-Die Delay Variations Kazuya KATSUKI Manabu KOTANI Kazutoshi KOBAYASHI Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/04/01 Vol. E90-C No. 4 pp. 699-707 Type of Manuscript: Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies) Category: Digital Keyword: within-die variation, reconfigurable device, FPGA, LUT (look-up table), yield,
	Summary \| Full Text:PDF (664.2KB)

A Systolic FPGA Architecture of Two-Level Dynamic Programming for Connected Speech Recognition Yong KIM Hong JEONG
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2007/02/01 Vol. E90-D No. 2 pp. 562-568 Type of Manuscript: PAPER Category: Speech and Hearing Keyword: speech recognition, hidden Markov model (HMM), two-level dynamic programming (TLDP), FPGA,
	Summary \| Full Text:PDF (660.4KB)

Compact Numerical Function Generators Based on Quadratic Approximation: Architecture and Synthesis Method Shinobu NAGAYAMA Tsutomu SASAO Jon T. BUTLER
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/12/01 Vol. E89-A No. 12 pp. 3510-3518 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Circuit Synthesis Keyword: LUT cascades, 2nd-order Chebyshev approximation, non-uniform segmentation, NFGs, automatic synthesis, FPGA,
	Summary \| Full Text:PDF (308.8KB)

Implementation of Multi-Channel Modem for DSRC System on Signal Processing Platform for Software Defined Radio Akihisa YOKOYAMA Hiroshi HARADA
Publication: IEICE TRANSACTIONS on Communications Publication Date: 2006/12/01 Vol. E89-B No. 12 pp. 3225-3232 Type of Manuscript: Special Section PAPER (Special Section on Software Defined Radio Technology and Its Applications) Category: Keyword: software defined radio, signal processing, FPGA, ITS, DSRC,
	Summary \| Full Text:PDF (928.7KB)

Joint Hardware-Software Implementation of Adaptive Array Antenna for ISDB-T Reception Dang Hai PHAM Takanobu TABATA Hirokazu ASATO Satoshi HORI Tomohisa WADA
Publication: IEICE TRANSACTIONS on Communications Publication Date: 2006/12/01 Vol. E89-B No. 12 pp. 3215-3224 Type of Manuscript: Special Section PAPER (Special Section on Software Defined Radio Technology and Its Applications) Category: Keyword: array antenna, OFDM, ISDB-T, MRC, SMI, FPGA, DSP,
	Summary \| Full Text:PDF (1.1MB)

Fast FPGA-Emulation-Based Simulation Environment for Custom Processors Yuichi NAKAMURA Kouhei HOSOKAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/12/01 Vol. E89-A No. 12 pp. 3464-3470 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Simulation and Verification Keyword: custom processor, simulation, emulation, FPGA,
	Summary \| Full Text:PDF (1.5MB)

Design and Evaluation of Data-Dependent Hardware for AES Encryption Algorithm Ryoichiro ATONO Shuichi ICHIKAWA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2006/07/01 Vol. E89-D No. 7 pp. 2301-2305 Type of Manuscript: LETTER Category: VLSI Systems Keyword: FPGA, custom circuit, partial evaluation, specialization, cryptography, embedded system,
	Summary \| Full Text:PDF (116.4KB)

Partially-Parallel LDPC Decoder Achieving High-Efficiency Message-Passing Schedule Kazunori SHIMIZU Tatsuyuki ISHIKAWA Nozomu TOGAWA Takeshi IKENAGA Satoshi GOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/04/01 Vol. E89-A No. 4 pp. 969-978 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: low-density parity-check codes, partially-parallel LDPC decoder, message-passing algorithm, FPGA,
	Summary \| Full Text:PDF (749.1KB)

Low-Power Low-Leakage FPGA Design Using Zigzag Power Gating, Dual-V_TH/V_DD and Micro-V_DD-Hopping Canh Quang TRAN Hiroshi KAWAGUCHI Takayasu SAKURAI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2006/03/01 Vol. E89-C No. 3 pp. 280-286 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design Technology in the Sub-100 nm Era) Category: Low Power Techniques Keyword: FPGA, low power, low leakage, V_DD hopping, Zigzag power-gating,
	Summary \| Full Text:PDF (953.5KB)

A Design of AES Encryption Circuit with 128-bit Keys Using Look-Up Table Ring on FPGA Hui QIN Tsutomu SASAO Yukihiro IGUCHI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2006/03/01 Vol. E89-D No. 3 pp. 1139-1147 Type of Manuscript: PAPER Category: Computer Components Keyword: AES encryption, pipelined partial rolling (PPR), FPGA,
	Summary \| Full Text:PDF (1.3MB)

A Coarse-Grain Hierarchical Technique for 2-Dimensional FFT on Configurable Parallel Computers Xizhen XU Sotirios G. ZIAVRAS
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2006/02/01 Vol. E89-D No. 2 pp. 639-646 Type of Manuscript: Special Section PAPER (Special Section on Parallel/Distributed Computing and Networking) Category: Parallel/Distributed Algorithms Keyword: configurable computing, FPGA, SIMD, parallel processing, memory switching, FFT, hardware-software codesign,
	Summary \| Full Text:PDF (418.9KB)

Design and Evaluation of Hardware Pseudo-Random Number Generator MT19937 Shiro KONUMA Shuichi ICHIKAWA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2005/12/01 Vol. E88-D No. 12 pp. 2876-2879 Type of Manuscript: LETTER Category: VLSI Systems Keyword: custom circuit, simulation, random number, Mersenne Twister, FPGA,
	Summary \| Full Text:PDF (105.7KB)

Low-Power Field-Programmable VLSI Using Multiple Supply Voltages Weisheng CHONG Masanori HARIYAMA Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/12/01 Vol. E88-A No. 12 pp. 3298-3305 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Low Power Methodology Keyword: reconfigurable processor, FPGA, multiple-supply-voltage scheme,
	Summary \| Full Text:PDF (924.7KB)

FPGA Implementation of a Stereo Matching Processor Based on Window-Parallel-and-Pixel-Parallel Architecture Masanori HARIYAMA Yasuhiro KOBAYASHI Haruka SASAKI Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/12/01 Vol. E88-A No. 12 pp. 3516-3522 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: VLSI Architecture Keyword: stereo vision, FPGA, scheduling, allocation,
	Summary \| Full Text:PDF (813.5KB)

Frequency-Scaling Approach for Managing Power Consumption in NOCs Chun-Lung HSU Wen-Tso WANG Ying-Fu HONG
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/12/01 Vol. E88-A No. 12 pp. 3580-3583 Type of Manuscript: Special Section LETTER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: frequency-scaling, low power, NOC, FPGA,
	Summary \| Full Text:PDF (487.9KB)

A Reconfigurable Packet Routing-Oriented Signal Processing Platform Akihisa YOKOYAMA Hitoshi INOUE Hiroshi HARADA
Publication: IEICE TRANSACTIONS on Communications Publication Date: 2005/11/01 Vol. E88-B No. 11 pp. 4194-4203 Type of Manuscript: Special Section PAPER (Special Section on Software Defined Radio Technology and Its Applications) Category: Keyword: software defined radio, signal processing, FPGA, DSRC,
	Summary \| Full Text:PDF (1.9MB)

A Novel FPGA Architecture and an Integrated Framework of CAD Tools for Implementing Applications Konstantinos SIOZIOS George KOUTROUMPEZIS Konstantinos TATAS Nikolaos VASSILIADIS Vasilios KALENTERIDIS Haroula POURNARA Ilias PAPPAS Dimitrios SOUDRIS Antonios THANAILAKIS Spiridon NIKOLAIDIS Stilianos SISKOS
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2005/07/01 Vol. E88-D No. 7 pp. 1369-1380 Type of Manuscript: Special Section PAPER (Special Section on Recent Advances in Circuits and Systems--Part 1) Category: Programmable Logic, VLSI, CAD and Layout Keyword: FPGA, circuit design, CAD tools, RTL design, configuration bitstream,
	Summary \| Full Text:PDF (1.3MB)

Header Extraction and Control for an Asynchronous Optical Packet Switch Based on DPSK Decoding Dimitrios KLONIDIS Christina T. POLITI Reza NEJABATI Mike J. O'MAHONY Dimitra SIMEONIDOU
Publication: IEICE TRANSACTIONS on Communications Publication Date: 2005/05/01 Vol. E88-B No. 5 pp. 1876-1883 Type of Manuscript: Special Section PAPER (Joint Special Section on Recent Progress in Optoelectronics and Communications) Category: Optical Network Architecture Keyword: optical packet switching, optical DPSK, switch control, FPGA,
	Summary \| Full Text:PDF (1.1MB)

FPGAs with Multidimensional Switch Topology Yohei MATSUMOTO Akira MASAKI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2005/04/01 Vol. E88-D No. 4 pp. 775-778 Type of Manuscript: LETTER Category: VLSI Systems Keyword: FPGA, multidimensional topology, number of switches, Rent's rule,
	Summary \| Full Text:PDF (77.3KB)

FPGA-Based Reconfigurable Adaptive FEC Kazunori SHIMIZU Jumpei UCHIDA Yuichiro MIYAOKA Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/12/01 Vol. E87-A No. 12 pp. 3036-3046 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: System Level Design Keyword: dynamic reconfigurable system, adaptive FEC, FPGA, Reed Solomon codes,
	Summary \| Full Text:PDF (493.3KB)

Field-Programmable VLSI Based on a Bit-Serial Fine-Grain Architecture Masanori HARIYAMA Weisheng CHONG Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2004/11/01 Vol. E87-C No. 11 pp. 1897-1902 Type of Manuscript: Special Section PAPER (Special Section on New System Paradigms for Integrated Electronics) Category: Keyword: reconfigurable architecture, FPGA, bit-serial architecture,
	Summary \| Full Text:PDF (530.6KB)

Self-Reconfigurable Multi-Layer Neural Networks with Genetic Algorithms Eiko SUGAWARA Masaru FUKUSHI Susumu HORIGUCHI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2004/08/01 Vol. E87-D No. 8 pp. 2021-2028 Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems) Category: Recornfigurable Systems Keyword: self-reconfiguration, multi-layer neural network, weight training by genetic algorithm, FPGA,
	Summary \| Full Text:PDF (597.7KB)

Preliminary Evaluation of Flex Power FPGA: A Power Reconfigurable Architecture with Fine Granularity Takashi KAWANAMI Masakazu HIOKI Hiroshi NAGASE Toshiyuki TSUTSUMI Tadashi NAKAGAWA Toshihiro SEKIGAWA Hanpei KOIKE
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2004/08/01 Vol. E87-D No. 8 pp. 2004-2010 Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems) Category: Recornfigurable Systems Keyword: FPGA, reconfigurable device, low-power, threshold voltage control, EDA,
	Summary \| Full Text:PDF (2.2MB)

A Real-Time Image Compressor Using 2-Dimensional DWT and Its FPGA Implementation Young-Ho SEO Wang-Hyun KIM Ji-Sang YOO Dai-Gyoung KIM Dong-Wook KIM
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/08/01 Vol. E87-A No. 8 pp. 2110-2119 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: DWT, wavelet, compression, FPGA, design, hardware,
	Summary \| Full Text:PDF (1.4MB)

The Design and Evaluation of Data-Dependent Hardware for Subgraph Isomorphism Problem Shoji YAMAMOTO Shuichi ICHIKAWA Hiroshi YAMAMOTO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2004/08/01 Vol. E87-D No. 8 pp. 2038-2047 Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems) Category: Recornfigurable Systems Keyword: FPGA, custom circuit, graph algorithm, NP-complete, partial evaluation,
	Summary \| Full Text:PDF (472.2KB)

An FPGA-Based Acceleration Method for Metabolic Simulation Yasunori OSANA Tomonori FUKUSHIMA Masato YOSHIMI Hideharu AMANO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2004/08/01 Vol. E87-D No. 8 pp. 2029-2037 Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems) Category: Recornfigurable Systems Keyword: metabolic simulation, ordinary differential equations, FPGA,
	Summary \| Full Text:PDF (546KB)

An Acceleration Processor for Data Intensive Scientific Computing Cheong Ghil KIM Hong-Sik KIM Sungho KANG Shin Dug KIM Gunhee HAN
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2004/07/01 Vol. E87-D No. 7 pp. 1766-1773 Type of Manuscript: Special Section PAPER (Special Section on Hardware/Software Support for High Performance Scientific and Engineering Computing) Category: Scientific and Engineering Computing with Applications Keyword: SIMD, FPGA, artificial neural networks, diffusion equations, image processing,
	Summary \| Full Text:PDF (1.1MB)

FPGA Design of Real-Time Watermarking Processor for 2DDWT-Based Video Compression Young-Ho SEO Dong-Wook KIM
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/06/01 Vol. E87-A No. 6 pp. 1297-1304 Type of Manuscript: Special Section PAPER (Special Section on Papers Selected from 2003 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2003)) Category: Keyword: image watermarking, DWT, FPGA, hardware implementation, co-operation with compressor,
	Summary \| Full Text:PDF (558.4KB)

An Equalization Technique for 54 Mbps OFDM Systems Naihua YUAN Anh DINH Ha H. NGUYEN
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/03/01 Vol. E87-A No. 3 pp. 610-618 Type of Manuscript: Special Section PAPER (Special Section on Applications and Implementations of Digital Signal Processing) Category: Communication Theory and Systems Keyword: time domain equalization, OFDM, LDL^T and LU decompositions, IEEE 802.11a, FPGA, pipeline FFT,
	Summary \| Full Text:PDF (623.5KB)

Feasibility Study on Over-the-Air Software Download for Software-Radio-Based Intelligent Transport Systems Hiroshi HARADA Masayuki FUJISE
Publication: IEICE TRANSACTIONS on Communications Publication Date: 2003/12/01 Vol. E86-B No. 12 pp. 3425-3432 Type of Manuscript: Special Section PAPER (Special Issue on Software Defined Radio Technology and Its Applications) Category: Keyword: software radio, ITS, over-the-air download, FPGA, multimode terminal,
	Summary \| Full Text:PDF (1.4MB)

Trade-Offs in Custom Circuit Designs for Subgraph Isomorphism Problems Shuichi ICHIKAWA Hidemitsu SAITO Lerdtanaseangtham UDORN Kouji KONISHI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2003/07/01 Vol. E86-D No. 7 pp. 1250-1257 Type of Manuscript: PAPER Category: VLSI Systems Keyword: NP-complete, graph, algorithm, FPGA,
	Summary \| Full Text:PDF (328KB)

Data Dependent Circuit for Subgraph Isomorphism Problem Shuichi ICHIKAWA Shoji YAMAMOTO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2003/05/01 Vol. E86-D No. 5 pp. 796-802 Type of Manuscript: Special Section PAPER (Special Issue on Reconfigurable Computing) Category: Keyword: NP-complete, custom circuit, FPGA, graph algorithm,
	Summary \| Full Text:PDF (260.4KB)

Time-Memory Trade-off Cryptanalysis for Limited Key on FPGA-Based Parallel Machine RASH Katsumi TAKAHASHI Hiroai ASAMI Katsuto NAKAJIMA Masahiro IIDA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2003/05/01 Vol. E86-D No. 5 pp. 781-788 Type of Manuscript: Special Section PAPER (Special Issue on Reconfigurable Computing) Category: Keyword: RASH, FPGA, reconfigurable computing, time-memory trade-off cryptanalysis,
	Summary \| Full Text:PDF (599.6KB)

An Efficient Algorithm Finding Simple Disjoint Decompositions Using BDDs Yusuke MATSUNAGA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2002/12/01 Vol. E85-A No. 12 pp. 2715-2724 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis Keyword: functional decomposition, BDDs, logic synthesis, FPGA,
	Summary \| Full Text:PDF (298.5KB)

Adaptive Burst M-QAM Modem Architecture for Broadband Wireless Applications Daniel T. ASPEL David M. KLYMYSHYN
Publication: IEICE TRANSACTIONS on Communications Publication Date: 2002/12/01 Vol. E85-B No. 12 pp. 2760-2763 Type of Manuscript: Special Section LETTER (Special Issue on Software Defined Radio Technology and Its Applications) Category: Keyword: M-QAM, adaptive modulation, FPGA, software defined radio (SDR),
	Summary \| Full Text:PDF (405.2KB)

Random Number Generators Implemented with Neighborhood-of-Four, Non-locally Connected Cellular Automata Barry SHACKLEFORD Motoo TANAKA Richard J. CARTER Greg SNIDER
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2002/12/01 Vol. E85-A No. 12 pp. 2612-2623 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: VLSI Design Keyword: random number generator, cellular automata, FPGA,
	Summary \| Full Text:PDF (1.3MB)

Configurable and Reconfigurable Computing for Digital Signal Processing Toshinori SUEYOSHI Masahiro IIDA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2002/03/01 Vol. E85-A No. 3 pp. 591-599 Type of Manuscript: INVITED PAPER (Special Section on the Trend of Digital Signal Processing and Its Future Direction) Category: LSI/Signal Processors Keyword: configurable computing, reconfigurable computing, digital signal processing, FPGA,
	Summary \| Full Text:PDF (1.1MB)

Implementation of a High-Performance Genetic Algorithm Processor for Hardware Optimization Jinjung KIM Yunho CHOI Chongho LEE Duckjin CHUNG
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2002/01/01 Vol. E85-C No. 1 pp. 195-203 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: genetic algorithm (GA), FPGA, optimization,
	Summary \| Full Text:PDF (1MB)

The Kernel-Based Pattern Recognition System Designed by Genetic Algorithms Moritoshi YASUNAGA Taro NAKAMURA Ikuo YOSHIHARA Jung Hwan KIM
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2001/11/01 Vol. E84-D No. 11 pp. 1528-1539 Type of Manuscript: Special Section PAPER (Special Issue on Function Integrated Information Systems) Category: Keyword: genetic algorithm, FPGA, pattern recognition, reconfigurable system, kernel-based method,
	Summary \| Full Text:PDF (2MB)

The Evolutionary Algorithm-Based Reasoning System Moritoshi YASUNAGA Ikuo YOSHIHARA Jung Hwan KIM
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2001/11/01 Vol. E84-D No. 11 pp. 1508-1520 Type of Manuscript: Special Section PAPER (Special Issue on Function Integrated Information Systems) Category: Keyword: evolutionary algorithm, reasoning, FPGA, wafer scale integration, fault tolerance,
	Summary \| Full Text:PDF (2.5MB)

Design of FIR Digital Filters with CSD Coefficients Having Power-of-Two DC Gain and Their FPGA Implementation for Minimum Critical Path Mitsuru YAMADA Akinori NISHIHARA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2001/08/01 Vol. E84-A No. 8 pp. 1997-2003 Type of Manuscript: PAPER Category: Digital Signal Processing Keyword: FIR digital filters, CSD, optimization, integer programming, FPGA,
	Summary \| Full Text:PDF (898.1KB)

An Efficient Routing Algorithm for Symmetrical FPGAs Using Reliable Cost Metrics Nak-Woong EUM Inhag PARK Chong-Min KYUNG
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2001/03/01 Vol. E84-A No. 3 pp. 829-838 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: FPGA, routing, routability, delay,
	Summary \| Full Text:PDF (708.1KB)

Delay-Optimal Technology Mapping for Hard-Wired Non-Homogeneous FPGAs Hsien-Ho CHUANG Jing-Yang JOU C. Bernard SHUNG
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2000/12/20 Vol. E83-A No. 12 pp. 2545-2551 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Performance Optimization Keyword: technology mapping, FPGA, hard-wired, non-homogeneous, XC4000,
	Summary \| Full Text:PDF (325.3KB)

A New FPGA Architecture for High Performance Bit-Serial Pipeline Datapath Akihisa OHTA Tsuyoshi ISSHIKI Hiroaki KUNIEDA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2000/08/20 Vol. E83-A No. 8 pp. 1663-1672 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: FPGA, bit-serial, logic block architecture, routing architecture, logic utilization, Rent's rule, chip scalability,
	Summary \| Full Text:PDF (1.6MB)

Design of DS1 Transport Device in SDH Network Yeong-Gang SHOW Kuo-Bing CHOU Jim WANG Kou-Tan WU
Publication: IEICE TRANSACTIONS on Communications Publication Date: 2000/07/20 Vol. E83-B No. 7 pp. 1389-1399 Type of Manuscript: PAPER Category: Fiber-Optic Transmission Keyword: SDH, SONET, DS1, TU-11 mapper, FPGA,
	Summary \| Full Text:PDF (1.9MB)

A Study on the Design of VME System Controller Kang Hyeon RHEE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2000/06/20 Vol. E83-A No. 6 pp. 1083-1090 Type of Manuscript: Special Section PAPER (Special Section of Papers Selected from 1999 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC'99)) Category: Keyword: factory automaton, VME system controller, VHDL, FPGA,
	Summary \| Full Text:PDF (1.5MB)

CORDIC-Based Direct Digital Frequency Synthesizer: Comparison with a ROM-Based Architecture in FPGA Implementation Minkyoung PARK Kiseon KIM Jeong-A LEE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2000/06/20 Vol. E83-A No. 6 pp. 1282-1285 Type of Manuscript: LETTER Category: Digital Signal Processing Keyword: CORDIC, DDFS (Direct Digital Frequency Synthesizer), sine generation, FPGA,
	Summary \| Full Text:PDF (278.8KB)

A Software Antenna: Reconfigurable Adaptive Arrays Based on Eigenvalue Decomposition Yukihiro KAMIYA Yoshio KARASAWA Satoshi DENNO Yoshihiko MIZUGUCHI
Publication: IEICE TRANSACTIONS on Communications Publication Date: 1999/12/20 Vol. E82-B No. 12 pp. 2012-2020 Type of Manuscript: Special Section PAPER (Special Issue on Multimedia Mobile Communication Systems) Category: Keyword: software antenna, DBF, FPGA, DSP, multipath fading,
	Summary \| Full Text:PDF (579.6KB)

Simplified Routing Procedure for a CAD-Verified FPGA Takahiro MUROOKA Atsushi TAKAHARA Toshiaki MIYAZAKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1999/11/20 Vol. E82-A No. 11 pp. 2440-2447 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: FPGA, CAD algorithms, routing,
	Summary \| Full Text:PDF (1MB)

FPGA-Based Hash Circuit Synthesis with Evolutionary Algorithms Ernesto DAMIANI Valentino LIBERALI Andrea G. B. TETTAMANZI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1999/09/20 Vol. E82-A No. 9 pp. 1888-1896 Type of Manuscript: Special Section PAPER (Special Section on Nonlinear Theory and Its Applications) Category: Keyword: evolvable hardware, evolutionary algorithms, nonlinear circuit synthesis, FPGA,
	Summary \| Full Text:PDF (961.7KB)

A Method for Circular Pattern Recognition in a Binary Image and Its Implementation onto an FPGA Yusuke TOKUNAGA Takahiro INOUE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1999/02/20 Vol. E82-A No. 2 pp. 246-254 Type of Manuscript: Special Section PAPER (Special Section on VLSI for Digital Signal Processing) Category: Keyword: pattern recognition, template matching, digital hardware implementation, FPGA,
	Summary \| Full Text:PDF (491.7KB)

200-ps Interchip-Delay Field-Programmable MCM for Telecommunications Masaru KATAYAMA Takahiro MUROOKA Toshiaki MIYAZAKI Kazuhiro SHIRAKAWA Kazuhiro HAYASHI Takaki ICHIMORI Kennosuke FUKAMI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1998/12/20 Vol. E81-A No. 12 pp. 2673-2678 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: FPGA, MCM, Interchip delay,
	Summary \| Full Text:PDF (801.5KB)

A Neural-Greedy Combination Algorithm for Board-Level Routing in FPGA-Based Logic Emulation Systems Nobuo FUNABIKI Junji KITAMICHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1998/05/20 Vol. E81-A No. 5 pp. 866-872 Type of Manuscript: Special Section PAPER (Special Section on Discrete Mathematics and Its Applications) Category: Keyword: FPGA, board-level routing, NP-complete, digital neural network, greedy algorithm,
	Summary \| Full Text:PDF (544.8KB)

An FPGA Layout Reconfiguration Algorithm Based on Global Routes for Engineering Changes in System Design Specifications Nozomu TOGAWA Kayoko HAGI Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1998/05/20 Vol. E81-A No. 5 pp. 873-884 Type of Manuscript: Special Section PAPER (Special Section on Discrete Mathematics and Its Applications) Category: Keyword: FPGA, engineering change, layout reconfiguration, placement and routing,
	Summary \| Full Text:PDF (968.2KB)

Routability of FPGAs with Extremal Switch-Block Structures Yasuhiro TAKASHIMA Atsushi TAKAHASHI Yoji KAJITANI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1998/05/20 Vol. E81-A No. 5 pp. 850-856 Type of Manuscript: Special Section PAPER (Special Section on Discrete Mathematics and Its Applications) Category: Keyword: FPGA, switch-block, routability, detailed-routing,
	Summary \| Full Text:PDF (584.6KB)

Computational Complexity Analysis of Set-Bin-Packing Problem Tomonori IZUMI Toshihiko YOKOMARU Atsushi TAKAHASHI Yoji KAJITANI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1998/05/20 Vol. E81-A No. 5 pp. 842-849 Type of Manuscript: Special Section PAPER (Special Section on Discrete Mathematics and Its Applications) Category: Keyword: bin-packing, complexity, technology mapping, FPGA,
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Flexible Hardware Design Methodology for High-Performance ATM Switching System Using Real-Time Emulation Technique Tsuneo MATSUMURA Naoaki YAMANAKA Ryoichi YAMAGUCHI Keiji ISHIKAWA
Publication: IEICE TRANSACTIONS on Communications Publication Date: 1998/02/20 Vol. E81-B No. 2 pp. 466-472 Type of Manuscript: Special Section PAPER (Special Issue on ATM Switching Systems for future B-ISDN) Category: Advanced technologies for ATM system Keyword: ATM switching system, LU, emulation, FPGA, interconnect device,
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Design of a Two-Dimensional Digital Chaos Circuit Realizing a Henon Map Kei EGUCHI Takahiro INOUE Akio TSUNEDA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1998/01/20 Vol. E81-C No. 1 pp. 78-81 Type of Manuscript: LETTER Category: Electronic Circuits Keyword: chaos circuits, digital circuits, discrete-time circuits, integrated circuits, FPGA,
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Delay Calculation Method for SRAM-based FPGAs Masaru KATAYAMA Atsushi TAKAHARA Toshiaki MIYAZAKI Kennosuke FUKAMI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1997/10/20 Vol. E80-A No. 10 pp. 1789-1794 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: FPGA, propagation delay, CAD,
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Logic Synthesis for Cellular Architecture FPGAs Using EXOR Ternary Decision Diagrams Gueesang LEE Sungju PARK
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1997/10/20 Vol. E80-A No. 10 pp. 1820-1825 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: logic synthesis, FPGA, Cellular architetcture, Maitra terms, ETDO,
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A Co-Evaluation of the Architectures and the CAD System for Speed-Oriented FPGAs Tsunemasa HAYASHI Atsushi TAKAHARA Kennosuke FUKAMI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1997/10/20 Vol. E80-A No. 10 pp. 1842-1852 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: FPGA, telecommunications, multiplexor-type logic cell, BDD-based technology mapping, clustered wiring structure,
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Routability Analysis of Bit-Serial Pipeline Datapaths Tsuyoshi ISSHIKI Wayne Wei-Ming DAI Hiroaki KUNIEDA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1997/10/20 Vol. E80-A No. 10 pp. 1861-1870 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: bit-serial pipeline, Rent's rule, routability, FPGA,
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Logic Synthesis for Look-Up Table Based FPGAs Using Functional Decomposition and Boolean Resubstitution Hiroshi SAWADA Takayuki SUYAMA Akira NAGOYA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1997/10/20 Vol. E80-D No. 10 pp. 1017-1023 Type of Manuscript: Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design) Category: Logic Design Keyword: FPGA, look-up table (LUT), functional decomposition, Boolean resubstitution, support minimization,
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A performance-Oriented Simultaneous Placement and Global Routing Algorithm for Transport-Processing FPGAs Nozomu TOGAWA Masao SATO Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1997/10/20 Vol. E80-A No. 10 pp. 1795-1806 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: FPGA, transport processing, layout design, placement and routing, performance optimization, circuit delay,
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A Circuit Partitioning Algorithm with Path Delay Constraints for Multi-FPGA Systems Nozomu TOGAWA Masao SATO Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1997/03/20 Vol. E80-A No. 3 pp. 494-505 Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 9th Karuizawa Workshop on Circuits and Systems) Category: Keyword: FPGA, multi-FPGA system, circuit partitioning, path delay, logic-block replication,
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Inverter Reduction Algorithm for Super Fine-Grain Parallel Processing Hideyuki ITO Kouichi NAGAMI Tsunemichi SHIOZAWA Kiyoshi OGURI Yukihiro NAKAMURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1997/03/20 Vol. E80-A No. 3 pp. 487-493 Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 9th Karuizawa Workshop on Circuits and Systems) Category: Keyword: super fine-grain parallel processing, FPGA, high level synthesize PARTHENON, inverter reduction, dynamical system,
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Implementation of a Digital Signal Processor in a DBF Self-Beam-Steering Array Antenna Toyohisa TANAKA Ryu MIURA Yoshio KARASAWA
Publication: IEICE TRANSACTIONS on Communications Publication Date: 1997/01/20 Vol. E80-B No. 1 pp. 166-175 Type of Manuscript: PAPER Category: Antennas and Propagation Keyword: DBF antenna, self-beam-steering, self-phasing, maximal ratio combining, DSP, FPGA, ASIC,
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Simultaneous Placement and Global Routing for Transport-Processing FPGA Layout Nozumu TOGAWA Masao SATO Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1996/12/20 Vol. E79-A No. 12 pp. 2140-2150 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: FPGA, transport processing, layout design, placement and routing network flow,
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Technology Mapping for FPGAs with Composite Logic Block Architectures Hsien-Ho CHUANG C. Bernard SHUNG
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1996/10/20 Vol. E79-D No. 10 pp. 1396-1404 Type of Manuscript: Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design) Category: Logic Synthesis Keyword: technology mapping, FPGA, subject graph, pattern graph,
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A Simultaneous Technology Mapping, Placement, and Global Routing Algorithm for FPGAs with Path Delay Constraints Nozomu TOGAWA Masao SATO Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1996/03/20 Vol. E79-A No. 3 pp. 321-329 Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 8th Karuizawa Workshop on Circuits and Systems) Category: Keyword: FPGA, technology mapping, layout, path delay, performance optimization,
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A Circuit Partitioning Algorithm with Replication Capability for Multi-FPGA Systems Nozomu TOGAWA Masao SATO Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1995/12/20 Vol. E78-A No. 12 pp. 1765-1776 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: FPGA, circuit partitioning, logic-block replication, network flow,
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Maple: A Simultaneous Technology Mapping, Placement, and Global Routing Algorithm for Field-Programmable Gate Arrays Nozomu TOGAWA Masao SATO Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1994/12/20 Vol. E77-A No. 12 pp. 2028-2038 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: FPGA, look up table, technology mapping, layout design, placement, global routing,
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Design of a Reconfigurable Parallel Processor for Digital Control Using FPGAs Yoshichika FUJIOKA Michitaka KAMEYAMA Nobuhiro TOMABECHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1994/07/20 Vol. E77-C No. 7 pp. 1123-1130 Type of Manuscript: Special Section PAPER (Special Issue on Super Chip for Intelligent Integrated Systems) Category: Keyword: delay time, multi-operand multiply-addition, reconfiguration, digital control, FPGA,
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Reconfigurable Machine and its Application to Logic Simulation Nasahiro TOMITA Naoaki SUGANUMA Kotaro HIRANO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1993/10/20 Vol. E76-A No. 10 pp. 1705-1712 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: reconfigurable machine, logic simulation, FPGA, hardware accelerator,
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