Keyword : ECL-CMOS SRAM

Design of a 2-ns Cycle Time 72-kb ECL-CMOS SRAM Macro
Kenichi OHHATA  Takeshi KUSUNOKI  Hiroaki NAMBU  Kazuo KANETANI  Keiichi HIGETA  Kunihiko YAMAGUCHI  Noriyuki HOMMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/03/20
Vol. E81-C  No. 3  pp. 447-454
Type of Manuscript: PAPER
Category: Integrated Electronics
Keyword: 
high-speed SRAM,  ECL-CMOS SRAM,  write pulse generator, 
  Summary |  Full Text:PDF (767.6KB)
Redundancy Circuit for a Sub-nanosecond, Megabit ECL-CMOSSRAM
Kenichi OHHATA  Takeshi KUSUNOKI  Hiroaki NAMBU  Kazuo KANETANI  Toru MASUDA  Masayuki OHAYASHI  Satomi HAMAMOTO  Kunihiko YAMAGUCHI  Youji IDEI  Noriyuki HOMMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/03/20
Vol. E79-C  No. 3  pp. 415-423
Type of Manuscript: PAPER
Category: Integrated Electronics
Keyword: 
redundancy,  ECL-CMOS SRAM,  SRAM with logic gate,  BiCMOS, 
  Summary |  Full Text:PDF (894.3KB)
Noise Reduction Techniques for a 64-kb ECL-CMOS SRAM with a 2-ns Cycle Time
Kenichi OHHATA  Yoshiaki SAKURAI  Hiroaki NAMBU  Kazuo KANETANI  Youji IDEI  Toshirou HIRAMOTO  Nobuo TAMBA  Kunihiko YAMAGUCHI  Masanori ODAKA  Kunihiko WATANABE  Takahide IKEDA  Noriyuki HOMMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/11/20
Vol. E76-C  No. 11  pp. 1611-1619
Type of Manuscript: Special Section PAPER (Special Issue on LSI Memories)
Category: SRAM
Keyword: 
ECL-CMOS SRAM,  64-kb,  noise reduction,  crosstalk, 
  Summary |  Full Text:PDF (915.2KB)