Keyword : DSP processor

A Retargetable Simulator Generator for DSP Processor Cores with Packed SIMD-type Instructions
Nozomu TOGAWA  Kyosuke KASAHARA  Yuichiro MIYAOKA  Jinku CHOI  Masao YANAGISAWA  Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12  pp. 3099-3109
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Simulation Accelerator
Keyword: 
retargetable simulator,  DSP processor,  packed SIMD type instruction,  hardware/software cosynthesis,  processor synthesis, 
  Summary |  Full Text:PDF (855.5KB)
A Hardware/Software Partitioning Algorithm for Processor Cores with Packed SIMD-Type Instructions
Nozomu TOGAWA  Koichi TACHIKAKE  Yuichiro MIYAOKA  Masao YANAGISAWA  Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12  pp. 3218-3224
Type of Manuscript: Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: Design Methodology
Keyword: 
processor synthesis,  packed SIMD type instruction,  hardware/software partitioning,  hardware/software cosynthesis,  DSP processor, 
  Summary |  Full Text:PDF (407.8KB)
A Reconfigurable Digital Signal Processor
Boon Keat TAN  Toru OGAWA  Ryuji YOSHIMURA  Kenji TANIGUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/09/20
Vol. E81-C  No. 9  pp. 1424-1430
Type of Manuscript: Special Section PAPER (Special Issue on Novel VLSI Processor Architectures)
Category: 
Keyword: 
DSP processor,  reconfigurable,  flexible,  processors array,  fault-tolerant,  ASIC,  digital signal processing,  RISC, 
  Summary |  Full Text:PDF (742KB)