Keyword : DRAM


Energy-Efficient DRAM Selective Refresh Technique with Page Residence in a Memory Hierarchy of Hardware-Managed TLB
Miseon HAN Yeoul NA Dongha JUNG Hokyoon LEE Seon WOOK KIM Youngsun HAN 
Publication:   
Publication Date: 2018/03/01
Vol. E101-C  No. 3 ; pp. 170-182
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
DRAMselective refreshpower reductionEDP
 Summary | Full Text:PDF(1MB)

Power-Efficient Instancy Aware DRAM Scheduling
Gung-Yu PAN Chih-Yen LAI Jing-Yang JOU Bo-Cheng Charles LAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2015/04/01
Vol. E98-A  No. 4 ; pp. 942-953
Type of Manuscript:  PAPER
Category: Systems and Control
Keyword: 
DRAMdynamic power managementenergy-aware systemsscheduling
 Summary | Full Text:PDF(1.5MB)

Small-Sized Leakage-Controlled Gated Sense Amplifier for 0.5-V Multi-Gigabit DRAM Arrays
Akira KOTABE Riichiro TAKEMURA Yoshimitsu YANAGAWA Tomonori SEKIGUCHI Kiyoo ITOH 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/04/01
Vol. E95-C  No. 4 ; pp. 594-599
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
DRAMlow voltagesense amplifiermid-point sensing
 Summary | Full Text:PDF(2.3MB)

An Area-Efficient, Low-VDD, Highly Reliable Multi-Cell Antifuse System Fully Operative in DRAMs
Jong-Pil SON Jin Ho KIM Woo Song AHN Seung Uk HAN Satoru YAMADA Byung-Sick MOON Churoo PARK Hong-Sun HWANG Seong-Jin JANG Joo Sun CHOI Young-Hyun JUN Soo-Won KIM 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/10/01
Vol. E94-C  No. 10 ; pp. 1690-1697
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
DRAMantifuserepairpost-package repairrecovery
 Summary | Full Text:PDF(1.8MB)

Adaptive Circuits for the 0.5-V Nanoscale CMOS Era
Kiyoo ITOH Masanao YAMAOKA Takashi OSHIMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/03/01
Vol. E93-C  No. 3 ; pp. 216-233
Type of Manuscript:  INVITED PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration)
Category: 
Keyword: 
minimum operating voltageSRAMDRAMFD-SOIFinFET
 Summary | Full Text:PDF(2.2MB)

DRAM Controller with a Complete Predictor
Vladimir V. STANKOVIC Nebojsa Z. MILENKOVIC 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2009/04/01
Vol. E92-D  No. 4 ; pp. 584-593
Type of Manuscript:  PAPER
Category: Computer Systems
Keyword: 
DRAMlatencyDRAM controllerpredictor
 Summary | Full Text:PDF(422.3KB)

Reliable Cache Architectures and Task Scheduling for Multiprocessor Systems
Makoto SUGIHARA Tohru ISHIHARA Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/04/01
Vol. E91-C  No. 4 ; pp. 410-417
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories)
Category: 
Keyword: 
single event upsetSRAMDRAMreliabilitycache architecturetask scheduling
 Summary | Full Text:PDF(558.2KB)

Low-Voltage Embedded RAMs in Nanometer Era
Takayuki KAWAHARA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/04/01
Vol. E90-C  No. 4 ; pp. 735-742
Type of Manuscript:  INVITED PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies)
Category: 
Keyword: 
low-voltageSRAMDRAMFD-SOItwin-cellembedded RAM
 Summary | Full Text:PDF(1.1MB)

A Capacitorless Twin-Transistor Random Access Memory (TTRAM) on SOI
Fukashi MORISHITA Hideyuki NODA Isamu HAYASHI Takayuki GYOHTEN Mako OKAMOTO Takashi IPPOSHI Shigeto MAEGAWA Katsumi DOSAKA Kazutami ARIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/04/01
Vol. E90-C  No. 4 ; pp. 765-771
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies)
Category: Memory
Keyword: 
SOIcapacitorlessDRAMlow powerdata retention
 Summary | Full Text:PDF(932.3KB)

A Reliability-Enhanced TCAM Architecture with Associated Embedded DRAM and ECC
Hideyuki NODA Katsumi DOSAKA Hans Jurgen MATTAUSCH Tetsushi KOIDE Fukashi MORISHITA Kazutami ARIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/11/01
Vol. E89-C  No. 11 ; pp. 1612-1619
Type of Manuscript:  Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies)
Category: 
Keyword: 
soft errorECCTCAMembeddedDRAM
 Summary | Full Text:PDF(1.2MB)

A Study of Sense-Voltage Margins in Low-Voltage-Operating Embedded DRAM Macros
Akira YAMAZAKI Fukashi MORISHITA Naoya WATANABE Teruhiko AMANO Masaru HARAGUCHI Hideyuki NODA Atsushi HACHISUKA Katsumi DOSAKA Kazutami ARIMOTO Setsuo WAKE Hideyuki OZAKI Tsutomu YOSHIHARA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/10/01
Vol. E88-C  No. 10 ; pp. 2020-2027
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
embedded memoryDRAMvoltage marginlow voltagesystem on chip
 Summary | Full Text:PDF(908.3KB)

Highly Flexible Row and Column Redundancy and Cycle Time Adaptive Read Data Path for Double Data Rate Synchronous Memories
Kiyohiro FURUTANI Takeshi HAMAMOTO Takeo MIKI Masaya NAKANO Takashi KONO Shigeru KIKUDA Yasuhiro KONISHI Tsutomu YOSHIHARA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/02/01
Vol. E88-C  No. 2 ; pp. 255-263
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
DRAMredundancyhigh speedhigh density
 Summary | Full Text:PDF(3.1MB)

Efficient and Large-Current-Output Boosted Voltage Generators with Non-Overlapping-Clock-Driven Auxiliary Pumps for Sub-1-V Memory Applications
Kyeong-Sik MIN Young-Hee KIM Daejeong KIM Dong Myeong KIM Jin-Hong AHN Jin-Yong CHUNG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/07/01
Vol. E87-C  No. 7 ; pp. 1208-1213
Type of Manuscript:  LETTER
Category: Electronic Circuits
Keyword: 
charge pumpsvoltage generatorsDRAMlow voltage
 Summary | Full Text:PDF(624.6KB)

A Low Power Embedded DRAM Macro for Battery-Operated LSIs
Takeshi FUJINO Akira YAMAZAKI Yasuhiko TAITO Mitsuya KINOSHITA Fukashi MORISHITA Teruhiko AMANO Masaru HARAGUCHI Makoto HATAKENAKA Atsushi AMO Atsushi HACHISUKA Kazutami ARIMOTO Hideyuki OZAKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12 ; pp. 2991-3000
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Power Optimization
Keyword: 
embedded memoryDRAMlow powersystem on chip
 Summary | Full Text:PDF(2.9MB)

A High-Endurance Read/Write Scheme for Half-Vcc Plate Nonvolatile DRAMs with Ferroelectric Capacitors
Hiroki FUJISAWA Takeshi SAKATA Tomonori SEKIGUCHI Kazuyoshi TORII Katsutaka KIMURA Kazuhiko KAJIGAYA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2001/06/01
Vol. E84-C  No. 6 ; pp. 763-770
Type of Manuscript:  Special Section PAPER (Special Issue on Nonvolatile Memories)
Category: FeRAMs
Keyword: 
DRAMferroelectric memoryhigh speedlow-powerhigh-endurance
 Summary | Full Text:PDF(775.3KB)

Architecture and Performance Evaluation of a New Functional Memory: Functional Memory for Addition
Kazutoshi KOBAYASHI Masanao YAMAOKA Yukifumi KOBAYASHI Hidetoshi ONODERA Keikichi TAMARU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/12/25
Vol. E83-A  No. 12 ; pp. 2400-2408
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: VLSI Architecture
Keyword: 
VLSIfunctional memoryDRAMparallel processorblock matching
 Summary | Full Text:PDF(868.6KB)

Design and Analysis of Resonant-Tunneling-Diode (RTD) Based High Performance Memory System
Tetsuya UEMURA Pinaki MAZUMDER 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/09/25
Vol. E82-C  No. 9 ; pp. 1630-1637
Type of Manuscript:  Special Section PAPER (Special Issue on Integrated Electronics and New System Paradigms)
Category: Application of Resonant Tunneling Devices
Keyword: 
resonant tunneling diodeDRAMsense amplifierinstabilityrefresh-free
 Summary | Full Text:PDF(736.4KB)

A Single Chip Multiprocessor Integrated with High Density DRAM
Tadaaki YAMAUCHI Lance HAMMOND Oyekunle A. OLUKOTUN Kazutami ARIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/08/25
Vol. E82-C  No. 8 ; pp. 1567-1577
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
DRAMoh-chip DRAMembedded DRAMon-chip L2 cachesSRAM cachesmultiprocessormultiprocessor-on-a-chip
 Summary | Full Text:PDF(437.7KB)

Advanced Characterization Method for Sub-Micron DRAM Cell Transistors
Ikuo KURACHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/04/25
Vol. E82-C  No. 4 ; pp. 618-623
Type of Manuscript:  Special Section PAPER (Special Issue on Microelectronic Test Structures)
Category: 
Keyword: 
DRAMcell transistorstest structureparameter extractionparasitic resistance
 Summary | Full Text:PDF(715.6KB)

Evaluation of Shared DRAM for Parallel Processor System with Shared Memory
Hiroyuki KURINO Keiichi HIRANO Taizo ONO Mitsumasa KOYANAGI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/12/25
Vol. E81-A  No. 12 ; pp. 2655-2660
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: LSI Architecture
Keyword: 
multiport memoryshared memoryparallel processor systemDRAM
 Summary | Full Text:PDF(693.6KB)

Evaluating DRAM Refresh Architectures for Merged DRAM/Logic LSIs
Taku OHSAWA Koji KAI Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/09/25
Vol. E81-C  No. 9 ; pp. 1455-1462
Type of Manuscript:  Special Section PAPER (Special Issue on Novel VLSI Processor Architectures)
Category: 
Keyword: 
DRAMDRAM refreshmerged DRAM/logicsystem LSIlow power
 Summary | Full Text:PDF(737.9KB)

The Analysis of the Stacked-Surrounding Gate Transistor (S-SGT) DRAM for the High Speed and Low Voltage Operation
Tetsuo ENDOH Katsuhisa SHINMEI Hiroshi SAKURABA Fujio MASUOKA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/09/25
Vol. E81-C  No. 9 ; pp. 1491-1498
Type of Manuscript:  PAPER
Category: Semiconductor Materials and Devices
Keyword: 
SGTS-SGTDRAMbit-line capacitance
 Summary | Full Text:PDF(763.9KB)

Application of Circuit-Level Hot-Carrier Reliability Simulation to Memory Design
Peter M. LEE Tsuyoshi SEO Kiyoshi ISE Atsushi HIRAISHI Osamu NAGASHIMA Shoji YOSHIDA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/04/25
Vol. E81-C  No. 4 ; pp. 595-601
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
hot-carrier degradationreliabilitydevice lifetimecircuit simulationSRAMDRAM
 Summary | Full Text:PDF(750KB)

A Board Level Parallel Test Circuit and a Short Circuit Failure Repair Circuit for High-Density, Low-Power DRAMs
Kiyohiro FURUTANI Tsukasa OOISHI Mikio ASAKURA Hideto HIDAKA Hideyuki OZAKI Michihiro YAMADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/04/25
Vol. E80-C  No. 4 ; pp. 582-589
Type of Manuscript:  Special Section PAPER (Special Issue on Circuit Technologies for Memory and Analog LSIs)
Category: 
Keyword: 
DRAMtestredundancy
 Summary | Full Text:PDF(642.9KB)

Hierarchical Word-Line Architecture for Large Capacity DRAMs
Tatsunori MUROTANI Tadahiko SUGIBAYASHI Masahide TAKADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/04/25
Vol. E80-C  No. 4 ; pp. 550-556
Type of Manuscript:  INVITED PAPER (Special Issue on Circuit Technologies for Memory and Analog LSIs)
Category: Memory LSI
Keyword: 
DRAMhierarchical word linepartial subarray activation
 Summary | Full Text:PDF(539.8KB)

Folded Bitline Architecture for a Gigabit-Scale NAND DRAM
Shinichiro SHIRATAKE Daisaburo TAKASHIMA Takehiro HASEGAWA Hiroaki NAKANO Yukihito OOWAKI Shigeyoshi WATANABE Takashi OHSAWA Kazunori OHUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/04/25
Vol. E80-C  No. 4 ; pp. 573-581
Type of Manuscript:  Special Section PAPER (Special Issue on Circuit Technologies for Memory and Analog LSIs)
Category: 
Keyword: 
DRAMcascadeNANDfolded bitlineopen bitlinedie sizenoise immunity
 Summary | Full Text:PDF(803.3KB)

Plate Bumping Leakage Current Measurement Method and Its Application to Data Retention Characteristic Analysis for RJB DRAM Cells
Toru IWATA Hiroyuki YAMAUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/12/25
Vol. E79-C  No. 12 ; pp. 1707-1712
Type of Manuscript:  Special Section PAPER (Special Issue on Low-Power LSI Technologies)
Category: 
Keyword: 
DRAMdata retentionmemory-cell leakage current
 Summary | Full Text:PDF(476.4KB)

A 250 mV Bit-Line Swing Scheme for 1-V Operating Gigabit Scale DRAMs
Tsuneo INABA Daisaburo TAKASHIMA Yukihito OOWAKI Tohru OZAKI Shigeyoshi WATANABE Takashi OHSAWA Kazunori OHUCHI Hiroyuki TANGO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/12/25
Vol. E79-C  No. 12 ; pp. 1699-1706
Type of Manuscript:  Special Section PAPER (Special Issue on Low-Power LSI Technologies)
Category: 
Keyword: 
DRAMpower dissipationreliabilitybit-linewordlinesmall swingthreshold voltagesense amplifiermemory cell
 Summary | Full Text:PDF(772.8KB)

NAND-Structured DRAM Cell with Lithography-Oriented Design
Masami AOKI Tohru OZAKI Takashi YAMADA Takeshi HAMAMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/06/25
Vol. E79-C  No. 6 ; pp. 792-797
Type of Manuscript:  Special Section PAPER (Special Issue on ULSI Memory Technology)
Category: Dynamic RAMs
Keyword: 
memoryDRAMstacked capacitor
 Summary | Full Text:PDF(744.7KB)

A Crossing Charge Recycle Refresh Scheme with a Separated Driver Sense-Amplifier for Gb DRAMs
Isao NARITAKE Tadahiko SUGIBAYASHI Satoshi UTSUGI Tatsunori MUROTANI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/06/25
Vol. E79-C  No. 6 ; pp. 787-791
Type of Manuscript:  Special Section PAPER (Special Issue on ULSI Memory Technology)
Category: Dynamic RAMs
Keyword: 
memoryDRAMhierarchical bit-linerefresh
 Summary | Full Text:PDF(494.5KB)

Improvement of Refresh Characteristics by SIMOX Technology for Giga-bit DRAMs
Takaho TANIGAWA Akira YOSHINO Hiroki KOGA Shuichi OHYA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/06/25
Vol. E79-C  No. 6 ; pp. 781-786
Type of Manuscript:  Special Section PAPER (Special Issue on ULSI Memory Technology)
Category: Dynamic RAMs
Keyword: 
refresh characteristicsdata retention timeSIMOXDRAM
 Summary | Full Text:PDF(574.1KB)

Features of SOI DRAM's and their Potential for Low-Voltage and/or Giga-Bit Scale DRAM's
Yasuo YAMAGUCHI Toshiyuki OASHI Takahisa EIMORI Toshiaki IWAMATSU Shouichi MITAMOTO Katsuhiro SUMA Takahiro TSURUDA Fukashi MORISHITA Masakazu HIROSE Hideto HIDAKA Kazutami ARIMOTO Kazuyasu FUJISHIMA Yasuo INOUE Tadashi NISHIMURA Hirokazu MIYOSHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/06/25
Vol. E79-C  No. 6 ; pp. 772-780
Type of Manuscript:  INVITED PAPER (Special Issue on ULSI Memory Technology)
Category: Dynamic RAMs
Keyword: 
SOLSIMOXDRAMlow-voltage operation
 Summary | Full Text:PDF(1MB)

Digital Delay Locked Loop and Design Technique for High-Speed Synchronous Interface
Yoshinori OKAJIMA Masao TAGUCHI Miki YANAGAWA Koichi NISHIMURA Osamu HAMADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/06/25
Vol. E79-C  No. 6 ; pp. 798-807
Type of Manuscript:  Special Section PAPER (Special Issue on ULSI Memory Technology)
Category: Dynamic RAMs
Keyword: 
DLLsynchronous interfaceDRAMbus timing skew
 Summary | Full Text:PDF(724.5KB)

Trends in High-Speed DRAM Architectures
Masaki KUMANOYA Toshiyuki OGAWA Yasuhiro KONISHI Katsumi DOSAKA Kazuhiro SHIMOTORI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/04/25
Vol. E79-C  No. 4 ; pp. 472-481
Type of Manuscript:  INVITED PAPER (Special Issue on Ultra-High-Speed LSIs)
Category: 
Keyword: 
reviewDRAMhigh-speed DRAMmain memorygraphics memoryperformance gapbandwidth bottleneckperformance comparisonhigh-speed I/O interfaceunified memorysystem integration
 Summary | Full Text:PDF(851.6KB)

Half-Vcc Plate Nonvolatile DRAMs with Ferroelectric Capacitors
Kan TAKEUCHI Katsumi MATSUNO Yoshinobu NAKAGOME Masakazu AOKI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/02/25
Vol. E79-C  No. 2 ; pp. 234-242
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
ferroelectric memoryDRAMhalf-V cc platenonvolatile memory
 Summary | Full Text:PDF(839.9KB)

NAND-Structured Trench Capacitor Cell Technologies for 256 Mb DRAM and Beyond
Takeshi HAMAMOTO Yutaka ISHIBASHI Masami AOKI Yoshihiko SAITOH Takashi YAMADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/07/25
Vol. E78-C  No. 7 ; pp. 789-796
Type of Manuscript:  Special Section PAPER (Special Issue on LSI Memory Device, Circuit, Architecture and Application Technologies for Multimedia Age)
Category: 
Keyword: 
memoryDRAMtrenchcapacitor
 Summary | Full Text:PDF(854.5KB)

New α-Particle Induced Soft Error Mechanism in a Three Dimensional Capacitor Cell
Yukihito OOWAKI Keiji MABUCHI Shigeyoshi WATANABE Kazunori OHUCHI Jun'ichi MATSUNAGA Fujio MASUOKA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/07/25
Vol. E78-C  No. 7 ; pp. 845-851
Type of Manuscript:  Special Section PAPER (Special Issue on LSI Memory Device, Circuit, Architecture and Application Technologies for Multimedia Age)
Category: 
Keyword: 
α-particlesoft errorDRAM
 Summary | Full Text:PDF(605.2KB)

A Synchronous DRAM with New High-Speed I/O Lines Method for the MultiMedia Age
Yuji SAKAI Kanji OISHI Miki MATSUMOTO Shoji WADA Tadamichi SAKASHITA Masahiro KATAYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/07/25
Vol. E78-C  No. 7 ; pp. 782-788
Type of Manuscript:  Special Section PAPER (Special Issue on LSI Memory Device, Circuit, Architecture and Application Technologies for Multimedia Age)
Category: 
Keyword: 
DRAMsynchronous operationmemory
 Summary | Full Text:PDF(554.4KB)

Emerging Memory Solutions for Graphics Applications
Katsumi SUIZU Toshiyuki OGAWA Kazuyasu FUJISHIMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/07/25
Vol. E78-C  No. 7 ; pp. 773-781
Type of Manuscript:  INVITED PAPER (Special Issue on LSI Memory Device, Circuit, Architecture and Application Technologies for Multimedia Age)
Category: 
Keyword: 
3D computer graphicstexture mappingZ-bufferbandwidth bottleneckDRAMsystem memoryframe bufferperformance comparison
 Summary | Full Text:PDF(741.6KB)

3-D CG Media Chip: An Experimental Single-Chip Architecture for Three-Dimensional Computer Graphics
Takao WATANABE Kazushige AYUKAWA Yoshinobu NAKAGOME 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/12/25
Vol. E77-C  No. 12 ; pp. 1881-1887
Type of Manuscript:  Special Section PAPER (Special Issue on Multimedia, Analog and Processing LSIs)
Category: Multimedia System LSIs
Keyword: 
media chipDRAM3-D computer graphics1.5-V operation0.35-µm CMOS design rule
 Summary | Full Text:PDF(614.5KB)

High-Speed Circuit Techniques for Battery-Operated 16 Mbit CMOS DRAM
Toshikazu SUZUKI Toru IWATA Hironori AKAMATSU Akihiro SAWADA Toshiaki TSUJI Hiroyuki YAMAUCHI Takashi TANIGUCHI Tsutomu FUJITA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/08/25
Vol. E77-C  No. 8 ; pp. 1334-1342
Type of Manuscript:  Special Section PAPER (Special Section on High Speed and High Density Multi Functional LSI Memories)
Category: DRAM
Keyword: 
DRAMcycle timebattery operatinghigh speed
 Summary | Full Text:PDF(832.9KB)

A Distributive Serial Multi-Bit Parallel Test Scheme for Large Capacity DRAMs
Tadahiko SUGIBAYASHI Isao NARITAKE Hiroshi TAKADA Ken INOUE Ichiro YAMAMOTO Tatsuya MATANO Mamoru FUJITA Yoshiharu AIMOTO Toshio TAKESHIMA Satoshi UTSUGI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/08/25
Vol. E77-C  No. 8 ; pp. 1323-1327
Type of Manuscript:  Special Section PAPER (Special Section on High Speed and High Density Multi Functional LSI Memories)
Category: DRAM
Keyword: 
memoryDRAMtest
 Summary | Full Text:PDF(588.5KB)

High Speed DRAMs with Innovative Architectures
Shigeo OHSHIMA Tohru FURUYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/08/25
Vol. E77-C  No. 8 ; pp. 1303-1315
Type of Manuscript:  INVITED PAPER (Special Section on High Speed and High Density Multi Functional LSI Memories)
Category: DRAM
Keyword: 
DRAMmemory bottleneckdata bandwidthlatencysynchronous DRAMpipeline architecturedata prefetchingcache DRAMfast copybackRambus interfaceRambus DRAMprotocol packetPLL
 Summary | Full Text:PDF(983.9KB)

Design Rule Relaxation Approach for High-Density DRAMs
Takanori SAEKI Eiichiro KAKEHASHI Hidemitu MORI Hiroki KOGA Kenji NODA Mamoru FUJITA Hiroshi SUGAWARA Kyoichi NAGATA Shozo NISHIMOTO Tatsunori MUROTANI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/03/25
Vol. E77-C  No. 3 ; pp. 406-415
Type of Manuscript:  Special Section PAPER (Special Issue on Quarter Micron Si Device and Process Technologies)
Category: Device Technology
Keyword: 
DRAMdesign ruleclose packed cell arrayBoosted Dual Word-Line scheme
 Summary | Full Text:PDF(1.1MB)

Soft-Error Study of DRAMs with Retrograde Well Structure by New Evaluation Method
Yoshikazu OHNO Hiroshi KIMURA Ken-ichiro SONODA Tadashi NISHIMURA Shin-ichi SATOH Hirokazu SAYAMA Shigenori HARA Mikio TAKAI Hirokazu MIYOSHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/03/25
Vol. E77-C  No. 3 ; pp. 399-405
Type of Manuscript:  Special Section PAPER (Special Issue on Quarter Micron Si Device and Process Technologies)
Category: Device Technology
Keyword: 
soft-errorDRAMmicroprobeprotonmapping
 Summary | Full Text:PDF(714.6KB)

(Ba0.75Sr0.25)TiO3 Films for 256 Mbit DRAM
Tsuyoshi HORIKAWA Noboru MIKAMI Hiromi ITO Yoshikazu OHNO Tetsuro MAKITA Kazunao SATO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/03/25
Vol. E77-C  No. 3 ; pp. 385-391
Type of Manuscript:  Special Section PAPER (Special Issue on Quarter Micron Si Device and Process Technologies)
Category: Device Technology
Keyword: 
(Ba,Sr)TiO3ferroelectricDRAMsputteringgrain size effect
 Summary | Full Text:PDF(701KB)

Application of KrF Excimer Laser Lithography to 256 MbDRAM Fabrication
Sin-ichi FUKUZAWA Hiroshi YOSHINO Shinji ISHIDA Kenji KONDOH Tsuyoshi YOSHII Naoaki AIZAKI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/11/25
Vol. E76-C  No. 11 ; pp. 1665-1669
Type of Manuscript:  Special Section LETTER (Special Issue on LSI Memories)
Category: Application Specific Memory
Keyword: 
DRAMKrF excimer laserlithography double-layer resisttriple-layer resist
 Summary | Full Text:PDF(698.4KB)

Trends in Capacitor Dielectrics for DRAMs
Akihiko ISHITANI Pierre-Yves LESAICHERRE Satoshi KAMIYAMA Koichi ANDO Hirohito WATANABE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/11/25
Vol. E76-C  No. 11 ; pp. 1564-1581
Type of Manuscript:  INVITED PAPER (Special Issue on LSI Memories)
Category: 
Keyword: 
capacitordielectricsSi3N4Ta2O5high permittivity materials256 Mbit1 GbitDRAM
 Summary | Full Text:PDF(1.8MB)

A Capacitor over Bit-Line (COB) Stacked Capacitor Cell Using Local Interconnect Layer for 64 MbDRAMs
Naoki KASAI Masato SAKAO Toshiyuki ISHIJIMA Eiji IKAWA Hirohito WATANABE Toshio TAKESHIMA Nobuhiro TANABE Kazuo TERADA Takamaro KIKKAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/04/25
Vol. E76-C  No. 4 ; pp. 548-555
Type of Manuscript:  Special Section PAPER (Special Issue on Sub-Half Micron Si Device and Process Technologies)
Category: Device Technology
Keyword: 
DRAMmemory cellstacked capacitorlocal interconnect
 Summary | Full Text:PDF(925.8KB)

Stabilization of Voltage Limiter Circuit for High-Density DRAM's Using Pole-Zero Compensation
Hitoshi TANAKA Masakazu AOKI Jun ETOH Masashi HORIGUCHI Kiyoo ITOH Kazuhiko KAJIGAYA Tetsurou MATSUMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1992/11/25
Vol. E75-C  No. 11 ; pp. 1333-1343
Type of Manuscript:  Special Section PAPER (Special Issue on LSI Memories)
Category: 
Keyword: 
memoryDRAMvoltage limiterpole-zero compensation
 Summary | Full Text:PDF(840.8KB)

ULSI Technology Trends toward 256K/1G DRAMs
Masahiro KASHIWAGI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1992/11/25
Vol. E75-C  No. 11 ; pp. 1304-1312
Type of Manuscript:  INVITED PAPER (Special Issue on LSI Memories)
Category: 
Keyword: 
ULSIDRAMtechnology trendSOIvertical processing
 Summary | Full Text:PDF(1MB)