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Keyword : DRAM
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Low-Voltage Embedded RAMs in Nanometer Era
Takayuki KAWAHARA
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Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2007/04/01
Vol. E90-C
No. 4
pp. 735-742
Type of Manuscript: Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies)
Category: INVITED
Keyword:
low-voltage,
SRAM,
DRAM,
FD-SOI,
twin-cell,
embedded RAM,
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Plate Bumping Leakage Current Measurement Method and Its Application to Data Retention Characteristic Analysis for RJB DRAM Cells
Toru IWATA
Hiroyuki YAMAUCHI
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Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 1996/12/20
Vol. E79-C
No. 12
pp. 1707-1712
Type of Manuscript: Special Section PAPER (Special Issue on Low-Power LSI Technologies)
Category:
Keyword:
DRAM,
data retention,
memory-cell leakage current,
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Summary |
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Trends in High-Speed DRAM Architectures
Masaki KUMANOYA
Toshiyuki OGAWA
Yasuhiro KONISHI
Katsumi DOSAKA
Kazuhiro SHIMOTORI
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Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 1996/04/20
Vol. E79-C
No. 4
pp. 472-481
Type of Manuscript: INVITED PAPER (Special Issue on Ultra-High-Speed LSIs)
Category:
Keyword:
review,
DRAM,
high-speed DRAM,
main memory,
graphics memory,
performance gap,
bandwidth bottleneck,
performance comparison,
high-speed I/O interface,
unified memory,
system integration,
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Emerging Memory Solutions for Graphics Applications
Katsumi SUIZU
Toshiyuki OGAWA
Kazuyasu FUJISHIMA
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Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 1995/07/20
Vol. E78-C
No. 7
pp. 773-781
Type of Manuscript: INVITED PAPER (Special Issue on LSI Memory Device, Circuit, Architecture and Application Technologies for Multimedia Age)
Category:
Keyword:
3D computer graphics,
texture mapping,
Z-buffer,
bandwidth bottleneck,
DRAM,
system memory,
frame buffer,
performance comparison,
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High Speed DRAMs with Innovative Architectures
Shigeo OHSHIMA
Tohru FURUYAMA
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Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 1994/08/20
Vol. E77-C
No. 8
pp. 1303-1315
Type of Manuscript: INVITED PAPER (Special Section on High Speed and High Density Multi Functional LSI Memories)
Category: DRAM
Keyword:
DRAM,
memory bottleneck,
data bandwidth,
latency,
synchronous DRAM,
pipeline architecture,
data prefetching,
cache DRAM,
fast copyback,
Rambus interface,
Rambus DRAM,
protocol packet,
PLL,
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