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Keyword : CMOS
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Economy Evaluation of Chip-PKG-Board Function Testing for Multi Pin LSI Packaging Hirobumi INOUE
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Publication: C - Abstracts of IEICE TRANSACTIONS on Electronics (Japanese Edition)
Publication Date: 2007/11/01
Vol. J90-C
No. 11
pp. 801-806
Type of Manuscript: Special Section PAPER (Special Issue on Next Generation High Density Packaging Materials Technology for High Performance Electric Systems)
Category: Keyword: testing,
CMOS,
LSI,
package,
multiple pins LSI,
economy evaluation,
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Summary |
Full Text(in Japanese):PDF
(683.3KB)
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A Compact Hamming Weight Comparator Cong-Kha PHAM
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Publication: A - Abstracts of IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences (Japanese Edition)
Publication Date: 2007/10/01
Vol. J90-A
No. 10
pp. 762-766
Type of Manuscript: LETTER
Category: Keyword: Hamming weight,
CMOS,
analog operation,
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Summary |
Full Text(in Japanese):PDF
(916.4KB)
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