Keyword : CMOS logic circuit


Low-Power Wiring Method for Band-Limited Signals in CMOS Logic Circuits by Segmentation Coding with Pseudo-Majority Voting
Katsuhiko UEDA Zuiko RIKUHASHI Kentaro HAYASHI Hiroomi HIKAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2015/04/01
Vol. E98-C  No. 4 ; pp. 356-363
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
CMOS logic circuitlow power consumptiondynamic power consumptionmajority votingbus-invert coding
 Summary | Full Text:PDF(2.1MB)

State-Dependence of On-Chip Power Distribution Network Capacitance
Koh YAMANAGA Shiho HAGIWARA Ryo TAKAHASHI Kazuya MASU Takashi SATO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2014/01/01
Vol. E97-C  No. 1 ; pp. 77-84
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
CMOS logic circuitstate-dependent capacitance modelcapacitance measurementPDN-capacitanceparasitic capacitance
 Summary | Full Text:PDF(2.2MB)

A Design Methodology for a DPA-Resistant Circuit with RSL Techniques
Daisuke SUZUKI Minoru SAEKI Koichi SHIMIZU Akashi SATOH Tsutomu MATSUMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/12/01
Vol. E93-A  No. 12 ; pp. 2497-2508
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
side-channel attacksdifferential power analysishardware countermeasurerandom switching logicCMOS logic circuit
 Summary | Full Text:PDF(2.2MB)

An Analysis of Leakage Factors for Dual-Rail Pre-Charge Logic Style
Daisuke SUZUKI Minoru SAEKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/01/01
Vol. E91-A  No. 1 ; pp. 184-192
Type of Manuscript:  Special Section PAPER (Special Section on Cryptography and Information Security)
Category: Side Channel Attacks
Keyword: 
side-channel attacksdifferential power analysishardware countermeasuredual-rail pre-charge logic styleCMOS logic circuit
 Summary | Full Text:PDF(584.6KB)

Leakage Analysis of DPA Countermeasures at the Logic Level
Minoru SAEKI Daisuke SUZUKI Tetsuya ICHIKAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/01/01
Vol. E90-A  No. 1 ; pp. 169-178
Type of Manuscript:  Special Section PAPER (Special Section on Cryptography and Information Security)
Category: Side Channel Attacks
Keyword: 
side-channel attacksdifferential power analysishardware countermeasureCMOS logic circuitsecond-order DPA
 Summary | Full Text:PDF(752.1KB)

Random Switching Logic: A New Countermeasure against DPA and Second-Order DPA at the Logic Level
Daisuke SUZUKI Minoru SAEKI Tetsuya ICHIKAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/01/01
Vol. E90-A  No. 1 ; pp. 160-168
Type of Manuscript:  Special Section PAPER (Special Section on Cryptography and Information Security)
Category: Side Channel Attacks
Keyword: 
side-channel attacksdifferential power analysishardware countermeasuresecond-order DPA random switching logicCMOS logic circuit
 Summary | Full Text:PDF(737.1KB)