Keyword : CMOS circuit

CMOS Circuit Simulation Using Latency Insertion Method
Tadatoshi SEKINE  Hideki ASAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/10/01
Vol. E92-A  No. 10  pp. 2546-2553
Type of Manuscript: Special Section PAPER (Special Section on Nonlinear Theory and its Applications)
Category: Nonlinear Problems
Keyword: 
latency insertion method,  CMOS circuit,  fast circuit simulation, 
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A 150 MS/s 10-bit CMOS Pipelined Subranging ADC with Time Constant Reduction Technique
Xian Ping FAN  Pak Kwong CHAN  Piew Yoong CHEE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/05/01
Vol. E92-C  No. 5  pp. 719-727
Type of Manuscript: PAPER
Category: Electronic Circuits
Keyword: 
analog-to-digital converter (ADC),  subranging ADC,  pipeline scheme,  CMOS integrated circuit,  switched-capacitor circuit,  CMOS circuit, 
  Summary |  Full Text:PDF
Comprehensive Matching Characterization of Analog CMOS Circuits
Hiroo MASUDA  Takeshi KIDA  Shin-ichi OHKAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/04/01
Vol. E92-A  No. 4  pp. 966-975
Type of Manuscript: Special Section PAPER (Special Section on Advanced Technologies Emerging Mainly from the 21st Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
mismatch,  small signal parameter,  CMOS circuit,  analog, 
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Analysis and Testing of Analog and Mixed-Signal Circuits by an Operation-Region Model
Yukiya MIURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/10/01
Vol. E85-D  No. 10  pp. 1551-1557
Type of Manuscript: Special Section PAPER (Special Issue on Test and Verification of VLSI)
Category: Analog/Mixed Signal Test
Keyword: 
abstract circuit model,  analog and mixed-signal circuits,  analysis and testing,  CMOS circuit,  operation region, 
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A Compact Radix-64 54 54 CMOS Redundant Binary Parallel Multiplier
Sang-Hoon LEE  Seung-Jun BAE  Hong-June PARK 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/06/01
Vol. E85-C  No. 6  pp. 1342-1350
Type of Manuscript: PAPER
Category: Electronic Circuits
Keyword: 
parallel multiplier,  redundant binary,  radix-64,  CMOS circuit,  digital circuit, 
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Power Estimation and Reduction of CMOS Circuits Considering Gate Delay
Hiroaki UEDA  Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1999/01/20
Vol. E82-D  No. 1  pp. 301-308
Type of Manuscript: PAPER
Category: Computer Systems
Keyword: 
CMOS circuit,  low power design,  gate delay,  transition probability,  switching activity, 
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A Design of High-Speed 4-2 Compressor for Fast Multiplier
Hiroshi MAKINO  Hiroaki SUZUKI  Hiroyuki MORINAKA  Yasunobu NAKASE  Hirofumi SHINOHARA  Koichiro MASHIKO  Tadashi SUMI  Yasutaka HORIBA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/04/20
Vol. E79-C  No. 4  pp. 538-548
Type of Manuscript: Special Section PAPER (Special Issue on Ultra-High-Speed LSIs)
Category: 
Keyword: 
4-2 compressor,  multiplier,  redundant binary,  transmission gate,  CMOS circuit, 
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Stuck–Open Fault Detection in CMOS Circuits Using Single Test Patterns
Enrico MACII  Qing XU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/11/20
Vol. E77-A  No. 11  pp. 1977-1979
Type of Manuscript: LETTER
Category: Computer Aided Design (CAD)
Keyword: 
CMOS circuit,  stuck–open fault,  test generation, 
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