Keyword : CDR


A 12.5Gbps CDR with Differential to Common Converting Edge Detector for the Wired and Wireless Serial Link
Kaoru KOHIRA Hiroki ISHIKURO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2016/04/01
Vol. E99-C  No. 4 ; pp. 458-465
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
CDRinjection lockingedge detectorshigh speed
 Summary | Full Text:PDF(1.9MB)

Relay Transmission Thruchip Interface with Low-Skew 3D Clock Distribution Network
Yasuhiro TAKE Tadahiro KURODA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2015/04/01
Vol. E98-C  No. 4 ; pp. 322-332
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design---Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
TCICoupled-resonator3-D Integration3-D clock distributionCDR
 Summary | Full Text:PDF(8.7MB)

A 10-Gb/s Burst-Mode Clock-and-Data Recovery IC with Frequency-Adjusting Dual Gated VCOs
Yusuke OHTOMO Masafumi NOGAWA Kazuyoshi NISHIMURA Shunji KIMURA Tomoaki YOSHIDA Tomoaki KAWAMURA Minoru TOGASHI Kiyomi KUMOZAKI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/06/01
Vol. E91-C  No. 6 ; pp. 903-910
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category: 
Keyword: 
PONburstCDRICCID
 Summary | Full Text:PDF(1.5MB)

A PVT Tolerant STM-16 Clock-and-Data Recovery LSI Using an On-Chip Loop-Gain Variation Compensation Architecture in 0.20-µm CMOS/SOI
Yusuke OHTOMO Hiroshi KOIZUMI Kazuyoshi NISHIMURA Masafumi NOGAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/04/01
Vol. E91-C  No. 4 ; pp. 655-661
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
LSICDRCMOSSOIjitter
 Summary | Full Text:PDF(1.6MB)

A Fully Integrated 1.7-3.125 Gbps Clock and Data Recovery Circuit Using a Gated Frequency Detector
Rong-Jyi YANG Shen-Iuan LIU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/08/01
Vol. E88-C  No. 8 ; pp. 1726-1730
Type of Manuscript:  Special Section PAPER (Special Section on Papers Selected from AP-ASIC 2004)
Category: 
Keyword: 
DLLCDRdual loop
 Summary | Full Text:PDF(1.3MB)

A Clock and Data Recovery PLL for Variable Bit Rate NRZ Data Using Adaptive Phase Frequency Detector
Gijun IDEI Hiroaki KUNIEDA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/06/01
Vol. E87-C  No. 6 ; pp. 956-963
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit and Device Technologies)
Category: 
Keyword: 
capture rangeCCOCDRclock and data recoveryfalse lockjitterNRZPFDPLLVCOz-domain analysis
 Summary | Full Text:PDF(1.8MB)

Novel 622 Mb/s Burst-Mode Clock and Data Recovery Circuits with Muxed Oscillators
Yu-Gun KIM Chun-Oh LEE Seung-Woo LEE Hyun-Su CHAI Hyun-Suk RYU Woo-Young CHOI 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2003/11/01
Vol. E86-B  No. 11 ; pp. 3288-3292
Type of Manuscript:  LETTER
Category: Communication Devices/Circuits
Keyword: 
burst-modePLLCDRPON
 Summary | Full Text:PDF(1.1MB)