Keyword : CAM


A Fast Updatable Implementation of Index Generation Functions Using Multiple IGUs
Tsutomu SASAO 
Publication:   
Publication Date: 2017/08/01
Vol. E100-D  No. 8 ; pp. 1574-1582
Type of Manuscript:  Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing)
Category: Logic Design
Keyword: 
random functionCAMcontent-addressable memorylinear decompositionlinear transformationstatistical analysisupdate method
 Summary | Full Text:PDF(477.4KB)

A Memory-Based IPv6 Lookup Architecture Using Parallel Index Generation Units
Hiroki NAKAHARA Tsutomu SASAO Munehiro MATSUURA Hisashi IWAMOTO Yasuhiro TERAO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2015/02/01
Vol. E98-D  No. 2 ; pp. 262-271
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Architecture
Keyword: 
CAMIP lookupindex generation unitFPGA
 Summary | Full Text:PDF(1MB)

A CAM-Based Information Detection Hardware System for Fast Image Matching on FPGA
Duc-Hung LE Tran-Bao-Thuong CAO Katsumi INOUE Cong-Kha PHAM 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2014/01/01
Vol. E97-C  No. 1 ; pp. 65-76
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
FPGAInformation Detection Hardware SystemCAMdual-port RAMmulti-matchimage matching
 Summary | Full Text:PDF(4.9MB)

Chromatic Adaptation Transform Using Mutual cRGB Adapting Degree for an Illuminant Correspondent Display
Sung-Hak LEE Kyu-Ik SOHNG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2013/11/01
Vol. E96-C  No. 11 ; pp. 1404-1407
Type of Manuscript:  BRIEF PAPER
Category: 
Keyword: 
CAMchromatic adaptationcorresponding colorincomplete adaptation
 Summary | Full Text:PDF(590.4KB)

A Virus Scanning Engine Using an MPU and an IGU Based on Row-Shift Decomposition
Hiroki NAKAHARA Tsutomu SASAO Munehiro MATSUURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/08/01
Vol. E96-D  No. 8 ; pp. 1667-1675
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Application
Keyword: 
pattern matchingvirus scanningindex generation functionCAM
 Summary | Full Text:PDF(1.1MB)

Software-Based Parallel Cryptographic Solution with Massive-Parallel Memory-Embedded SIMD Matrix Architecture for Data-Storage Systems
Takeshi KUMAKI Tetsushi KOIDE Hans Jurgen MATTAUSCH Masaharu TAGAMI Masakatsu ISHIZAKI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2011/09/01
Vol. E94-D  No. 9 ; pp. 1742-1754
Type of Manuscript:  PAPER
Category: Fundamentals of Information Systems
Keyword: 
matrix-processing architectureSIMDbit-serial and word-parallelCAMtable-lookup codingcryptographic algorithmAES
 Summary | Full Text:PDF(1.1MB)

Design of an 8-nsec 72-bit-Parallel-Search Content-Addressable Memory Using a Phase-Change Device
Satoru HANZAWA Takahiro HANYU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/08/01
Vol. E94-C  No. 8 ; pp. 1302-1310
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
content addressable memoryCAMparallel searchphase-change deviceone-hot codingnonvolatile memory
 Summary | Full Text:PDF(2.4MB)

Integration Architecture of Content Addressable Memory and Massive-Parallel Memory-Embedded SIMD Matrix for Versatile Multimedia Processor
Takeshi KUMAKI Masakatsu ISHIZAKI Tetsushi KOIDE Hans Jurgen MATTAUSCH Yasuto KURODA Takayuki GYOHTEN Hideyuki NODA Katsumi DOSAKA Kazutami ARIMOTO Kazunori SAITO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/09/01
Vol. E91-C  No. 9 ; pp. 1409-1418
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Processors Based on Novel Concepts in Computation)
Category: 
Keyword: 
content addressable memoryCAMmatrix-processing architectureSIMDbit-serial and word-paralleltable-lookup codingDCTHuffman codingJPEG
 Summary | Full Text:PDF(624KB)

A Low-Power Instruction Issue Queue for Microprocessors
Shingo WATANABE Akihiro CHIYONOBU Toshinori SATO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/04/01
Vol. E91-C  No. 4 ; pp. 400-409
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories)
Category: 
Keyword: 
microprocessorsinstruction schedulingCAMRAMlow-power
 Summary | Full Text:PDF(1.1MB)

Real-Time Huffman Encoder with Pipelined CAM-Based Data Path and Code-Word-Table Optimizer
Takeshi KUMAKI Yasuto KURODA Masakatsu ISHIZAKI Tetsushi KOIDE Hans Jurgen MATTAUSCH Hideyuki NODA Katsumi DOSAKA Kazutami ARIMOTO Kazunori SAITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2007/01/01
Vol. E90-D  No. 1 ; pp. 334-345
Type of Manuscript:  PAPER
Category: Image Processing and Video Processing
Keyword: 
content addressable memoryCAMHuffman codingparallel processingpipelinecode word table
 Summary | Full Text:PDF(2.1MB)

Scalable FPGA/ASIC Implementation Architecture for Parallel Table-Lookup-Coding Using Multi-Ported Content Addressable Memory
Takeshi KUMAKI Yutaka KONO Masakatsu ISHIZAKI Tetsushi KOIDE Hans Jurgen MATTAUSCH 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2007/01/01
Vol. E90-D  No. 1 ; pp. 346-354
Type of Manuscript:  PAPER
Category: Image Processing and Video Processing
Keyword: 
multiportcontent addressable memoryCAMparallel processingSIMDcategorizationbit parallel block paralleltable-lookup-codingHuffman coding
 Summary | Full Text:PDF(1.6MB)

A CAM-Based Signature-Matching Co-processor with Application-Driven Power-Reduction Features
Kazunari INOUE Hideyuki NODA Kazutami ARIMOTO Hans Jurgen MATTAUSCH Tetsushi KOIDE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/06/01
Vol. E88-C  No. 6 ; pp. 1332-1342
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
CAMTCAMsignature-matchingnetwork security
 Summary | Full Text:PDF(2.1MB)

Hierarchical Multi-Chip Architecture for High Capacity Scalability of Fully Parallel Hamming-Distance Associative Memories
Yusuke OIKE Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/11/01
Vol. E87-C  No. 11 ; pp. 1847-1855
Type of Manuscript:  Special Section PAPER (Special Section on New System Paradigms for Integrated Electronics)
Category: 
Keyword: 
associative memorycontent addressable memoryCAMHamming distancecapacity scalabilitymulti-chip structure
 Summary | Full Text:PDF(1.5MB)

An Innovative Architecture of CMAC
Kao-Shing HWANG Yuan-Pao HSU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/01/01
Vol. E87-C  No. 1 ; pp. 81-93
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
neural networkCMACCAMreconfigurable architecture
 Summary | Full Text:PDF(1.2MB)

FLASH: Fast and Scalable Table-Lookup Engine Architecture for Telecommunications
Tsunemasa HAYASHI Toshiaki MIYAZAKI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/10/01
Vol. E85-D  No. 10 ; pp. 1636-1644
Type of Manuscript:  PAPER
Category: Network
Keyword: 
table-lookupclassificationbest matchIPCAMprogrammable arbiter
 Summary | Full Text:PDF(407.2KB)

A High-Throughput VLSI Architecture for LZFG Data Compression
Jin-Ming CHEN Che-Ho WEI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/03/01
Vol. E85-D  No. 3 ; pp. 497-509
Type of Manuscript:  PAPER
Category: VLSI Systems
Keyword: 
LZFGLZ78Ziv-Lempeldata compressionCAM
 Summary | Full Text:PDF(2MB)

A Longest Match Table Look-up Method Using Pointer Cache
Masanori UGA Kohei SHIOMOTO 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2001/06/01
Vol. E84-B  No. 6 ; pp. 1664-1673
Type of Manuscript:  PAPER
Category: Internet
Keyword: 
longest matchCAMIPv6gigabit router
 Summary | Full Text:PDF(1.1MB)

Collision Detection VLSI Processor for Intelligent Vehicles Using a Hierarchically-Content-Addressable Memory
Masanori HARIYAMA Kazuhiro SASAKI Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/09/25
Vol. E82-C  No. 9 ; pp. 1722-1729
Type of Manuscript:  Special Section PAPER (Special Issue on Integrated Electronics and New System Paradigms)
Category: Processors
Keyword: 
hierarchical collision detectionarea-time product minimizationCAMpath planning
 Summary | Full Text:PDF(1.4MB)

Analog Circuit Design Methodology in a Low Power RISC Microprocessor
Koichiro ISHIBASHI Hisayuki HIGUCHI Toshinobu SHIMBO Kunio UCHIYAMA Kenji SHIOZAWA Naotaka HASHIMOTO Shuji IKEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/02/25
Vol. E81-A  No. 2 ; pp. 210-217
Type of Manuscript:  INVITED PAPER (Special Section on Analog Circuit Techniques in the Digital-Oriented Era)
Category: 
Keyword: 
microprocessorTLBCAM0. 35 µmCMOS
 Summary | Full Text:PDF(882.4KB)

CAM-Based Highly-Parallel Image Processing Hardware
Takeshi OGURA Mamoru NAKANISHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/07/25
Vol. E80-C  No. 7 ; pp. 868-874
Type of Manuscript:  INVITED PAPER (Special Issue on New Concept Device and Novel Architecture LSIs)
Category: 
Keyword: 
content addressable memoryCAMimage processinghighly-parallel processing
 Summary | Full Text:PDF(680KB)

Integrated Switching Architecture and Its Traffic Handling Capacity in Data Communication Networks
Noriharu MIYAHO Akira MIURA 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 1996/12/25
Vol. E79-B  No. 12 ; pp. 1887-1899
Type of Manuscript:  PAPER
Category: Communication Systems and Transmission Equipment
Keyword: 
packet switchingcircuit switchingATMhierarchical memory systemrandom time-slotCAM
 Summary | Full Text:PDF(979.2KB)

A 5-mW, 10-ns Cycle TLB Using a High-Performance CAM with Low-Power Match-Detection Circuits
Hisayuki HIGUCHI Suguru TACHIBANA Masataka MINAMI Takahiro NAGANO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/06/25
Vol. E79-C  No. 6 ; pp. 757-762
Type of Manuscript:  Special Section PAPER (Special Issue on ULSI Memory Technology)
Category: Static RAMs
Keyword: 
TLBCAMlow powerfully associative
 Summary | Full Text:PDF(624.5KB)