Keyword : CAD


FPGA Design Framework Combined with Commercial VLSI CAD
Qian ZHAO Kazuki INOUE Motoki AMAGASAKI Masahiro IIDA Morihiro KUGA Toshinori SUEYOSHI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/08/01
Vol. E96-D  No. 8 ; pp. 1602-1612
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Design Methodology
Keyword: 
FPGACADrouting
 Summary | Full Text:PDF(1.2MB)

Detection of Fundus Lesions Using Classifier Selection
Hiroto NAGAYOSHI Yoshitaka HIRAMATSU Hiroshi SAKO Mitsutoshi HIMAGA Satoshi KATO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2009/05/01
Vol. E92-D  No. 5 ; pp. 1168-1176
Type of Manuscript:  PAPER
Category: Biological Engineering
Keyword: 
fundusdiabetic retinopathyCADimage processingimage normalizationclassifier
 Summary | Full Text:PDF(1.4MB)

On the Computational Synthesis of CMOS Voltage Followers
Esteban TLELO-CUAUTLE Delia TORRES-MUÑOZ Leticia TORRES-PAPAQUI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12 ; pp. 3479-3484
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Circuit Synthesis
Keyword: 
CADanalog synthesisvoltage followernullatornoratorbiasing and sizingMOSFET
 Summary | Full Text:PDF(325.2KB)

SoC Architecture Synthesis Methodology Based on High-Level IPs
Michiaki MURAOKA Hiroaki NISHI Rafael K. MORIZAWA Hideaki YOKOTA Yoichi ONISHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12 ; pp. 3057-3067
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: System Level Design
Keyword: 
system level designarchitecture synthesishigh level IPCAD
 Summary | Full Text:PDF(3.7MB)

Substrate Coupling Simulation Suitable for Conventional CAD Tools
Tomohisa KIMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/02/01
Vol. E86-A  No. 2 ; pp. 419-423
Type of Manuscript:  Special Section LETTER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
substrate couplingsimulationmodelingCADtest chip
 Summary | Full Text:PDF(471.3KB)

A Hierarchical Circuit Clustering Algorithm with Stable Performance
Seung-June KYOUNG Kwang-Su SEONG In-Cheol PARK Chong-Min KYUNG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/09/25
Vol. E82-A  No. 9 ; pp. 1987-1993
Type of Manuscript:  LETTER
Category: VLSI Design Technology and CAD
Keyword: 
VLSICADpartitioningclustering
 Summary | Full Text:PDF(417.3KB)

SCR : SPICE Netlist Reduction Tool
Mototaka KURIBAYASHI Masaaki YAMADA Hideki TAKEUCHI Masami MURAKATA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/03/25
Vol. E82-A  No. 3 ; pp. 417-423
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 11th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
SPICEreductiontransistorsimulationCADVLSI
 Summary | Full Text:PDF(442.9KB)

Network Design and System Performance of FREDERICFile Retrieval Engineering on Distributed EnviRonment and Interactive Communication System
Mitsuru MIYAUCHI Masashi SHINONOME Kenzo TAKAHASHI Kouki MIYAZAWA 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 1998/12/25
Vol. E81-B  No. 12 ; pp. 2454-2460
Type of Manuscript:  Special Section PAPER (Special Issue on the Latest Development of Telecommunication Research)
Category: Network Design, Operation, and Management
Keyword: 
ISDNinternetCADcooperationfile transferdesk top video conference
 Summary | Full Text:PDF(1.2MB)

A New Routing Method Considering Neighboring-Wire Capacitance Constraints
Takumi WATANABE Kimihiro YAMAKOSHI Hitoshi KITAZAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/12/25
Vol. E81-A  No. 12 ; pp. 2679-2687
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
routingwire capacitancedeep-submicron designCADVLSI
 Summary | Full Text:PDF(839.1KB)

An Effective Routing Methodology for Gb/s LSIs Using Deep-Submicron Technology
Takumi WATANABE Yusuke OHTOMO Kimihiro YAMAKOSHI Yuichiro TAKEI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/04/25
Vol. E81-A  No. 4 ; pp. 677-684
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
routing methodologymaze routerlayoutCADVLSI
 Summary | Full Text:PDF(835KB)

A CAD-Based Low-Power Design Methodology for Very High-Speed Si Bipolar Standard Cell LSIs
Keiichi KOIKE Kenji KAWAI Akira ONOZAWA Yuichiro TAKEI Yoshiji KOBAYASHI Haruhiko ICHINO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/12/25
Vol. E80-C  No. 12 ; pp. 1578-1585
Type of Manuscript:  Special Section PAPER (Special Issue on Low-Power and High-Speed LSI Technologies)
Category: 
Keyword: 
Si bipolarECLstandard cellCADSDH
 Summary | Full Text:PDF(659.1KB)

An Efficient Method for The Derivation of Signal Flow Direction in Digital CMOS VLSI
Ahmed Riadh BABA-ALI Ahcene FARAH 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/10/25
Vol. E80-A  No. 10 ; pp. 1902-1907
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
VLSICADMOSswitch-levelsignal flow
 Summary | Full Text:PDF(537.4KB)

Delay Calculation Method for SRAM-based FPGAs
Masaru KATAYAMA Atsushi TAKAHARA Toshiaki MIYAZAKI Kennosuke FUKAMI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/10/25
Vol. E80-A  No. 10 ; pp. 1789-1794
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
FPGApropagation delayCAD
 Summary | Full Text:PDF(415KB)

A Balanced-Mesh Clock Routing Technique for Performance Improvement
Hidenori SATO Hiroaki MATSUDA Akira ONOZAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/08/25
Vol. E80-A  No. 8 ; pp. 1489-1495
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
LSICADlayout designclock skewpartitioningroutingMPEG2
 Summary | Full Text:PDF(592.3KB)

A New Rip-Up and Reroute Algorithm for Very Large Scale Gate Arrays
Hiroshi SHIROTA Satoshi SHIBATANI Masayuki TERAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/03/25
Vol. E80-A  No. 3 ; pp. 506-513
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 9th Karuizawa Workshop on Circuits and Systems)
Category: 
Keyword: 
multilayer routinglayoutCADVLSI
 Summary | Full Text:PDF(748.2KB)

Unified Process Flow Management System for ULSI Semiconductor Manufacturing
Etsuo FUKUDA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/03/25
Vol. E79-C  No. 3 ; pp. 282-289
Type of Manuscript:  Special Section PAPER (Special Issue on Scientific ULSI Manufacturing Technology)
Category: CIM/CAM
Keyword: 
CIMCADPDLprocess specificationsimulation
 Summary | Full Text:PDF(635.4KB)

Validation of UDL/I Test Suites and UDL/I Simulation/Synthesis Environment
Hiroyuki KANBARA Satoshi YOKOTA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/12/25
Vol. E78-A  No. 12 ; pp. 1749-1754
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
hardware description languagetest suitesvalidationCAD
 Summary | Full Text:PDF(434.3KB)

Synergistic Power/Area Optimization with Transistor Sizing and Wire Length Minimization
Masaaki YAMADA Sachiko KUROSAWA Reiko NOJIMA Naohito KOJIMA Takashi MITSUHASHI Nobuyuki GOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/04/25
Vol. E78-C  No. 4 ; pp. 441-446
Type of Manuscript:  Special Section PAPER (Special Issue on Low-Voltage, Low-Power Integrated Circuits)
Category: DA/Architecture
Keyword: 
LSIlayouttransistor sizinglow powerCAD
 Summary | Full Text:PDF(608.5KB)

A Hybrid Hierarchical Global Router for Multi-Layer VLSI's
Masayuki HAYASHI Shuji TSUKIYAMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/03/25
Vol. E78-A  No. 3 ; pp. 337-344
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 7th Karuizawa Workshop on Circuits and Systems)
Category: VLSI Design Technology and CAD
Keyword: 
hybrid hierarchical routerglobal routingmulti-layer routingCADVLSI
 Summary | Full Text:PDF(709.6KB)

A Global Router for Analog Function Blocks Based on the Branch-and-Bound Algorithm
Tadanao TSUBOTA Masahiro KAWAKITA Takahiro WATANABE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/03/25
Vol. E78-A  No. 3 ; pp. 345-352
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 7th Karuizawa Workshop on Circuits and Systems)
Category: VLSI Design Technology and CAD
Keyword: 
branch-and-boundlayoutglobal routingchannel-intersection graphanalogLSICAD
 Summary | Full Text:PDF(636.8KB)

The Concept of Tool-Based Direct Deformation Method for Networked Cooperative CAD Interface
Juli YAMASHITA Hiroshi YOKOI Yukio FUKUI Makoto SHIMOJO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1994/12/25
Vol. E77-D  No. 12 ; pp. 1350-1354
Type of Manuscript:  Special Section PAPER (Special Issue on Networked Reality)
Category: 
Keyword: 
CADVRCSCWdirect manipulationfree formTB-DDMtool
 Summary | Full Text:PDF(498.4KB)

Wire Length Expressions for Analytical Placement Approach
Shoichiro YAMADA Masahiro KASAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/04/25
Vol. E77-A  No. 4 ; pp. 716-718
Type of Manuscript:  LETTER
Category: Computer Aided Design (CAD)
Keyword: 
placementCADVLSI design
 Summary | Full Text:PDF(180.1KB)

A Hierarchical Global Router for Mscro-Block-Embedded Sea-of-Gates
Mototaka KURIBAYASHI Masaaki YAMADA Takashi MITSUHASHI Nobuyuki GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/10/25
Vol. E76-A  No. 10 ; pp. 1694-1704
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
VLSICADrouterhierarchical decomposition
 Summary | Full Text:PDF(1MB)

Optimization of Sequential Synchronous Digital Circuits Using Structural Models
Giovanni De MICHELI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/09/25
Vol. E76-D  No. 9 ; pp. 1018-1029
Type of Manuscript:  INVITED PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: Logic Synthesis
Keyword: 
computer hardware and disignsynchronous circuitsCADlogic synthesis
 Summary | Full Text:PDF(988.2KB)

Hierarchical Timing Analyzer for Multiple Phase Clocked Designs
Hiromi ISHIKAWA Masanori IMAI Junko KOBARA Shinichi MURAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/12/25
Vol. E75-A  No. 12 ; pp. 1732-1735
Type of Manuscript:  Special Section LETTER (Special Section on the 1992 IEICE Fall Conference)
Category: 
Keyword: 
timing analysistiming verificationstatic timing analysishierarchical timing analysissynchronous designCAD
 Summary | Full Text:PDF(288.5KB)

An Integrated MMIC CAD System
Takashi YAMADA Masao NISHIDA Tetsuro SAWAI Yasoo HARADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1992/06/25
Vol. E75-C  No. 6 ; pp. 656-662
Type of Manuscript:  Special Section PAPER (Special Issue on MMIC Technology)
Category: 
Keyword: 
microwavesimulationCADsystem
 Summary | Full Text:PDF(698.1KB)

Integrated Tools for Device Optimization
Massimo RUDAN Maria Cristina VECCHI Antonio GNUDI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1992/02/25
Vol. E75-C  No. 2 ; pp. 216-225
Type of Manuscript:  Special Section PAPER (Special Issue on Selected Papers from '91 VPAD)
Category: 
Keyword: 
CADoptimizationsemiconductor devices
 Summary | Full Text:PDF(921.6KB)