IEICE SEARCH SYSTEM

Keyword : BIST

A Delay Evaluation Circuit for Analog BIST Function Zhengliang LV Shiyuan YANG Hong WANG Linda MILOR
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2013/03/01 Vol. E96-C No. 3 pp. 393-401 Type of Manuscript: PAPER Category: Semiconductor Materials and Devices Keyword: delay testing, BIST, analog filter, sample-hold circuit,
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Built-In Self-Test for Static ADC Testing with a Triangle-Wave Incheol KIM Ingeol LEE Sungho KANG
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2013/02/01 Vol. E96-C No. 2 pp. 292-294 Type of Manuscript: BRIEF PAPER Category: Integrated Electronics Keyword: ADC, BIST, static test, triangle-wave,
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Pattern Mapping Method for Low Power BIST Based on Transition Freezing Method Youbean KIM Jaewon JANG Hyunwook SON Sungho KANG
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2010/03/01 Vol. E93-D No. 3 pp. 643-646 Type of Manuscript: LETTER Category: Dependable Computing Keyword: BIST, low power BIST, design for testability,
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A Low-Cost BIST Based on Histogram Testing for Analog to Digital Converters Kicheol KIM Youbean KIM Incheol KIM Hyeonuk SON Sungho KANG
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2008/04/01 Vol. E91-C No. 4 pp. 670-672 Type of Manuscript: LETTER Category: Semiconductor Materials and Devices Keyword: ADC testing, BIST, histogram testing,
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A Method of Locating Open Faults on Incompletely Identified Pass/Fail Information Koji YAMAZAKI Yuzo TAKAMATSU
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2008/03/01 Vol. E91-D No. 3 pp. 661-666 Type of Manuscript: Special Section PAPER (Special Section on Test and Verification of VLSIs) Category: Fault Diagnosis Keyword: fault diagnosis, open fault, BIST, pass/fail information,
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Effect of BIST Pretest on IC Defect Level Yoshiyuki NAKAMURA Jacob SAVIR Hideo FUJIWARA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2006/10/01 Vol. E89-D No. 10 pp. 2626-2636 Type of Manuscript: PAPER Category: Dependable Computing Keyword: BIST, fault coverage, defect level,
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Error Identification in At-Speed Scan BIST Environment in the Presence of Circuit and Tester Speed Mismatch Yoshiyuki NAKAMURA Thomas CLOUQUEUR Kewal K. SALUJA Hideo FUJIWARA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2006/03/01 Vol. E89-D No. 3 pp. 1165-1172 Type of Manuscript: PAPER Category: Dependable Computing Keyword: BIST, fault diagnosis, error identification, at-speed test, low speed tester,
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Channel-Count-Independent BIST for Multi-Channel SerDes Kouichi YAMAGUCHI Muneo FUKAISHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2006/03/01 Vol. E89-C No. 3 pp. 314-319 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design Technology in the Sub-100 nm Era) Category: Interface and Interconnect Techniques Keyword: SerDes, BIST, at-speed testing, PRBS, multi-channel synchronization,
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A Practical Analog BIST Cooperated with an LSI Tester Takanori KOMURO Naoto HAYASAKA Haruo KOBAYASHI Hiroshi SAKAYORI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/02/01 Vol. E89-A No. 2 pp. 465-468 Type of Manuscript: Special Section LETTER (Special Section on Analog Circuit Techniques and Related Topics) Category: Keyword: LSI testing, analog circuit, BIST, equivalent-time sampling, sampler,
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Deterministic Delay Fault BIST Using Adjacency Test Pattern Generation Kazuteru NAMBA Hideo ITO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2005/09/01 Vol. E88-D No. 9 pp. 2135-2142 Type of Manuscript: PAPER Category: Dependable Computing Keyword: two-pattern testing, adjacency test, deterministic test generation, BIST,
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An Effective Built-In Self-Test for Chargepump PLL Junseok HAN Dongsup SONG Hagbae KIM YoungYong KIM Sungho KANG
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2005/08/01 Vol. E88-C No. 8 pp. 1731-1733 Type of Manuscript: Special Section LETTER (Special Section on Papers Selected from AP-ASIC 2004) Category: Keyword: mixed-signal test, BIST, PLL,
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Defect Level vs. Yield and Fault Coverage in the Presence of an Unreliable BIST Yoshiyuki NAKAMURA Jacob SAVIR Hideo FUJIWARA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2005/06/01 Vol. E88-D No. 6 pp. 1210-1216 Type of Manuscript: PAPER Category: Dependable Computing Keyword: BIST, fault coverage, defect level,
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Application of High Quality Built-in Test Using Neighborhood Pattern Generator to Industrial Designs Kazumi HATAYAMA Michinobu NAKAO Yoshikazu KIYOSHIGE Koichiro NATSUME Yasuo SATO Takaharu NAGUMO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/12/01 Vol. E87-A No. 12 pp. 3318-3323 Type of Manuscript: Special Section LETTER (Special Section on VLSI Design and CAD Algorithms) Category: Test Keyword: BIST, test pattern generator, neighborhood pattern, LFSR, reseeding,
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Fault Diagnosis for RAMs Using Walsh Spectrum Atsumu ISENO Yukihiro IGUCHI Tsutomu SASAO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2004/03/01 Vol. E87-D No. 3 pp. 592-600 Type of Manuscript: Special Section PAPER (Special Section on Test and Verification of VLSI) Category: Memory Testing Keyword: memory test, diagnosis, BIST, fail-bitmap, Walsh spectrum,
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A Built-in Reseeding Technique for LFSR-Based Test Pattern Generation Youhua SHI Zhe ZHANG Shinji KIMURA Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/12/01 Vol. E86-A No. 12 pp. 3056-3062 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Timing Verification and Test Generation Keyword: reseeding, LFSR, BIST, test pattern generation,
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Seed Selection Procedure for LFSR-Based Random Pattern Generators Kenichi ICHINO Ko-ichi WATANABE Masayuki ARAI Satoshi FUKUMOTO Kazuhiko IWASAKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/12/01 Vol. E86-A No. 12 pp. 3063-3071 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Timing Verification and Test Generation Keyword: BIST, LFSR, test-per-clock, test-per-scan, seed, polynomial,
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An Embedded DRAM Hybrid Macro with Auto Signal Management and Enhanced-on-Chip Tester Naoya WATANABE Fukashi MORISHITA Yasuhiko TAITO Akira YAMAZAKI Tetsushi TANIZAKI Katsumi DOSAKA Yoshikazu MOROOKA Futoshi IGAUE Katsuya FURUE Yoshihiro NAGURA Tatsunori KOMOIKE Toshinori MORIHARA Atsushi HACHISUKA Kazutami ARIMOTO Hideyuki OZAKI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2003/04/01 Vol. E86-C No. 4 pp. 624-634 Type of Manuscript: Special Section PAPER (Special Issue on High-Performance, Low-Power System LSIs and Related Technologies) Category: Design Methods and Implementation Keyword: embedded DRAM, various DRAM macros, low voltage operation, short TAT, BIST,
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Deterministic Built-in Test with Neighborhood Pattern Generator Michinobu NAKAO Yoshikazu KIYOSHIGE Koichiro NATSUME Kazumi HATAYAMA Satoshi FUKUMOTO Kazuhiko IWASAKI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2002/05/01 Vol. E85-D No. 5 pp. 874-883 Type of Manuscript: PAPER Category: Fault Tolerance Keyword: BIST, test pattern generator, reseeding, bit-flipping, seed generation,
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Optimization of Test Accesses with a Combined BIST and External Test Scheme Makoto SUGIHARA Hiroto YASUURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2001/11/01 Vol. E84-A No. 11 pp. 2731-2738 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Test Keyword: test time, BIST, external test, CBET, test scheduling, test access, test bus, external pins,
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A Test Methodology for Core-Based System LSIs Makoto SUGIHARA Hiroshi DATE Hiroto YASUURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1998/12/20 Vol. E81-A No. 12 pp. 2640-2645 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Test Keyword: testing time, core-based system LSI, BIST, external testing,
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On Acceleration of Test Points Selection for Scan-Based BIST Michinobu NAKAO Kazumi HATAYAMA Isao HIGASHI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1998/07/20 Vol. E81-D No. 7 pp. 668-674 Type of Manuscript: Special Section PAPER (Special Issue on Test and Diagnosis of VLSI) Category: Built-in Self-Test Keyword: test points, BIST, optimization, testability,
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Exact Expected Test Length Generated by LFSRs for Circuits Containing Hard Random-Pattern-Resistant Faults Kazuhiko IWASAKI Hiroyuki GOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1998/05/20 Vol. E81-A No. 5 pp. 885-888 Type of Manuscript: Special Section LETTER (Special Section on Discrete Mathematics and Its Applications) Category: Keyword: BIST, test length, random-pattern-resistant fault, LFSR, integer partition problem,
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Analysis of Aliasing Probability for MISRs by Using Complete Weight Distributions Kazuhiko IWASAKI Sandeep K. GUPTA Prawat NAGVAJARA Tadao KASAMI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1995/12/20 Vol. E78-A No. 12 pp. 1691-1698 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: BIST, aliasing probability, error-correcting codes, complete weight distribution,
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BIST Circuit Macro Using Microprogram ROM for LSI Memories Hiroki KOIKE Toshio TAKESHIMA Masahide TAKADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1995/07/20 Vol. E78-C No. 7 pp. 838-844 Type of Manuscript: Special Section PAPER (Special Issue on LSI Memory Device, Circuit, Architecture and Application Technologies for Multimedia Age) Category: Keyword: memory, BIST, ROM, tester, macro,
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Comparison of Aliasing Probability for Multiple MISRs and M-Stage MISRs with m Inputs Kazuhiko IWASAKI Shou-Ping FENG Toru FUJIWARA Tadao KASAMI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1992/11/20 Vol. E75-D No. 6 pp. 835-841 Type of Manuscript: Special Section PAPER (Special Issue on Pacific Rim International Symposium on Fault Tolerant Systems) Category: Keyword: BIST, aliasing probability, multiple MISR, M-stage MISR with m imputs, binary symmetric channel,
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