Keyword : BIST


Scan-Out Power Reduction for Logic BIST
Senling WANG Yasuo SATO Seiji KAJIHARA Kohei MIYASE 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/09/01
Vol. E96-D  No. 9 ; pp. 2012-2020
Type of Manuscript:  Special Section PAPER (Special Section on Dependable Computing)
Category: 
Keyword: 
low powerBISTmulti-cycle testshift power
 Summary | Full Text:PDF(2.2MB)

A Delay Evaluation Circuit for Analog BIST Function
Zhengliang LV Shiyuan YANG Hong WANG Linda MILOR 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2013/03/01
Vol. E96-C  No. 3 ; pp. 393-401
Type of Manuscript:  PAPER
Category: Semiconductor Materials and Devices
Keyword: 
delay testingBISTanalog filtersample-hold circuit
 Summary | Full Text:PDF(5.1MB)

Built-In Self-Test for Static ADC Testing with a Triangle-Wave
Incheol KIM Ingeol LEE Sungho KANG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2013/02/01
Vol. E96-C  No. 2 ; pp. 292-294
Type of Manuscript:  BRIEF PAPER
Category: Integrated Electronics
Keyword: 
ADCBISTstatic testtriangle-wave
 Summary | Full Text:PDF(577.1KB)

Pattern Mapping Method for Low Power BIST Based on Transition Freezing Method
Youbean KIM Jaewon JANG Hyunwook SON Sungho KANG 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/03/01
Vol. E93-D  No. 3 ; pp. 643-646
Type of Manuscript:  LETTER
Category: Dependable Computing
Keyword: 
BISTlow power BISTdesign for testability
 Summary | Full Text:PDF(293.9KB)

A Low-Cost BIST Based on Histogram Testing for Analog to Digital Converters
Kicheol KIM Youbean KIM Incheol KIM Hyeonuk SON Sungho KANG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/04/01
Vol. E91-C  No. 4 ; pp. 670-672
Type of Manuscript:  LETTER
Category: Semiconductor Materials and Devices
Keyword: 
ADC testingBISThistogram testing
 Summary | Full Text:PDF(363.5KB)

A Method of Locating Open Faults on Incompletely Identified Pass/Fail Information
Koji YAMAZAKI Yuzo TAKAMATSU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/03/01
Vol. E91-D  No. 3 ; pp. 661-666
Type of Manuscript:  Special Section PAPER (Special Section on Test and Verification of VLSIs)
Category: Fault Diagnosis
Keyword: 
fault diagnosisopen faultBISTpass/fail information
 Summary | Full Text:PDF(570.7KB)

Effect of BIST Pretest on IC Defect Level
Yoshiyuki NAKAMURA Jacob SAVIR Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2006/10/01
Vol. E89-D  No. 10 ; pp. 2626-2636
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
BISTfault coveragedefect level
 Summary | Full Text:PDF(1.2MB)

Error Identification in At-Speed Scan BIST Environment in the Presence of Circuit and Tester Speed Mismatch
Yoshiyuki NAKAMURA Thomas CLOUQUEUR Kewal K. SALUJA Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2006/03/01
Vol. E89-D  No. 3 ; pp. 1165-1172
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
BISTfault diagnosiserror identificationat-speed testlow speed tester
 Summary | Full Text:PDF(462.4KB)

Channel-Count-Independent BIST for Multi-Channel SerDes
Kouichi YAMAGUCHI Muneo FUKAISHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/03/01
Vol. E89-C  No. 3 ; pp. 314-319
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design Technology in the Sub-100 nm Era)
Category: Interface and Interconnect Techniques
Keyword: 
SerDesBISTat-speed testingPRBSmulti-channel synchronization
 Summary | Full Text:PDF(657.5KB)

A Practical Analog BIST Cooperated with an LSI Tester
Takanori KOMURO Naoto HAYASAKA Haruo KOBAYASHI Hiroshi SAKAYORI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/02/01
Vol. E89-A  No. 2 ; pp. 465-468
Type of Manuscript:  Special Section LETTER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
LSI testinganalog circuitBISTequivalent-time samplingsampler
 Summary | Full Text:PDF(165.7KB)

Deterministic Delay Fault BIST Using Adjacency Test Pattern Generation
Kazuteru NAMBA Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/09/01
Vol. E88-D  No. 9 ; pp. 2135-2142
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
two-pattern testingadjacency testdeterministic test generationBIST
 Summary | Full Text:PDF(264.3KB)

An Effective Built-In Self-Test for Chargepump PLL
Junseok HAN Dongsup SONG Hagbae KIM YoungYong KIM Sungho KANG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/08/01
Vol. E88-C  No. 8 ; pp. 1731-1733
Type of Manuscript:  Special Section LETTER (Special Section on Papers Selected from AP-ASIC 2004)
Category: 
Keyword: 
mixed-signal testBISTPLL
 Summary | Full Text:PDF(559.7KB)

Defect Level vs. Yield and Fault Coverage in the Presence of an Unreliable BIST
Yoshiyuki NAKAMURA Jacob SAVIR Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/06/01
Vol. E88-D  No. 6 ; pp. 1210-1216
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
BISTfault coveragedefect level
 Summary | Full Text:PDF(629.9KB)

Application of High Quality Built-in Test Using Neighborhood Pattern Generator to Industrial Designs
Kazumi HATAYAMA Michinobu NAKAO Yoshikazu KIYOSHIGE Koichiro NATSUME Yasuo SATO Takaharu NAGUMO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12 ; pp. 3318-3323
Type of Manuscript:  Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: Test
Keyword: 
BISTtest pattern generatorneighborhood patternLFSRreseeding
 Summary | Full Text:PDF(429.3KB)

Fault Diagnosis for RAMs Using Walsh Spectrum
Atsumu ISENO Yukihiro IGUCHI Tsutomu SASAO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2004/03/01
Vol. E87-D  No. 3 ; pp. 592-600
Type of Manuscript:  Special Section PAPER (Special Section on Test and Verification of VLSI)
Category: Memory Testing
Keyword: 
memory testdiagnosisBISTfail-bitmapWalsh spectrum
 Summary | Full Text:PDF(717.5KB)

A Built-in Reseeding Technique for LFSR-Based Test Pattern Generation
Youhua SHI Zhe ZHANG Shinji KIMURA Masao YANAGISAWA Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12 ; pp. 3056-3062
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Timing Verification and Test Generation
Keyword: 
reseedingLFSRBISTtest pattern generation
 Summary | Full Text:PDF(1MB)

Seed Selection Procedure for LFSR-Based Random Pattern Generators
Kenichi ICHINO Ko-ichi WATANABE Masayuki ARAI Satoshi FUKUMOTO Kazuhiko IWASAKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12 ; pp. 3063-3071
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Timing Verification and Test Generation
Keyword: 
BISTLFSRtest-per-clocktest-per-scanseedpolynomial
 Summary | Full Text:PDF(673.3KB)

An Embedded DRAM Hybrid Macro with Auto Signal Management and Enhanced-on-Chip Tester
Naoya WATANABE Fukashi MORISHITA Yasuhiko TAITO Akira YAMAZAKI Tetsushi TANIZAKI Katsumi DOSAKA Yoshikazu MOROOKA Futoshi IGAUE Katsuya FURUE Yoshihiro NAGURA Tatsunori KOMOIKE Toshinori MORIHARA Atsushi HACHISUKA Kazutami ARIMOTO Hideyuki OZAKI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2003/04/01
Vol. E86-C  No. 4 ; pp. 624-634
Type of Manuscript:  Special Section PAPER (Special Issue on High-Performance, Low-Power System LSIs and Related Technologies)
Category: Design Methods and Implementation
Keyword: 
embedded DRAMvarious DRAM macroslow voltage operationshort TATBIST
 Summary | Full Text:PDF(5.2MB)

Deterministic Built-in Test with Neighborhood Pattern Generator
Michinobu NAKAO Yoshikazu KIYOSHIGE Koichiro NATSUME Kazumi HATAYAMA Satoshi FUKUMOTO Kazuhiko IWASAKI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/05/01
Vol. E85-D  No. 5 ; pp. 874-883
Type of Manuscript:  PAPER
Category: Fault Tolerance
Keyword: 
BISTtest pattern generatorreseedingbit-flippingseed generation
 Summary | Full Text:PDF(839.2KB)

Optimization of Test Accesses with a Combined BIST and External Test Scheme
Makoto SUGIHARA Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Vol. E84-A  No. 11 ; pp. 2731-2738
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Test
Keyword: 
test timeBISTexternal testCBETtest schedulingtest accesstest busexternal pins
 Summary | Full Text:PDF(720KB)

A Test Methodology for Core-Based System LSIs
Makoto SUGIHARA Hiroshi DATE Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/12/25
Vol. E81-A  No. 12 ; pp. 2640-2645
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Test
Keyword: 
testing timecore-based system LSIBISTexternal testing
 Summary | Full Text:PDF(584.1KB)

On Acceleration of Test Points Selection for Scan-Based BIST
Michinobu NAKAO Kazumi HATAYAMA Isao HIGASHI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/07/25
Vol. E81-D  No. 7 ; pp. 668-674
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Diagnosis of VLSI)
Category: Built-in Self-Test
Keyword: 
test pointsBISToptimizationtestability
 Summary | Full Text:PDF(672.2KB)

Exact Expected Test Length Generated by LFSRs for Circuits Containing Hard Random-Pattern-Resistant Faults
Kazuhiko IWASAKI Hiroyuki GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/05/25
Vol. E81-A  No. 5 ; pp. 885-888
Type of Manuscript:  Special Section LETTER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
BISTtest lengthrandom-pattern-resistant faultLFSRinteger partition problem
 Summary | Full Text:PDF(236.5KB)

Analysis of Aliasing Probability for MISRs by Using Complete Weight Distributions
Kazuhiko IWASAKI Sandeep K. GUPTA Prawat NAGVAJARA Tadao KASAMI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/12/25
Vol. E78-A  No. 12 ; pp. 1691-1698
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
BISTaliasing probabilityerror-correcting codescomplete weight distribution
 Summary | Full Text:PDF(591.2KB)

BIST Circuit Macro Using Microprogram ROM for LSI Memories
Hiroki KOIKE Toshio TAKESHIMA Masahide TAKADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/07/25
Vol. E78-C  No. 7 ; pp. 838-844
Type of Manuscript:  Special Section PAPER (Special Issue on LSI Memory Device, Circuit, Architecture and Application Technologies for Multimedia Age)
Category: 
Keyword: 
memoryBISTROMtestermacro
 Summary | Full Text:PDF(613.4KB)

Comparison of Aliasing Probability for Multiple MISRs and M-Stage MISRs with m Inputs
Kazuhiko IWASAKI Shou-Ping FENG Toru FUJIWARA Tadao KASAMI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1992/11/25
Vol. E75-D  No. 6 ; pp. 835-841
Type of Manuscript:  Special Section PAPER (Special Issue on Pacific Rim International Symposium on Fault Tolerant Systems)
Category: 
Keyword: 
BISTaliasing probabilitymultiple MISRM-stage MISR with m imputsbinary symmetric channel
 Summary | Full Text:PDF(578.4KB)