Keyword : BDD


Hardness Evaluation for Search LWE Problem Using Progressive BKZ Simulator
Yuntao WANG Yoshinori AONO Tsuyoshi TAKAGI 
Publication:   
Publication Date: 2018/12/01
Vol. E101-A  No. 12 ; pp. 2162-2170
Type of Manuscript:  Special Section PAPER (Special Section on Information Theory and Its Applications)
Category: Cryptography and Information Security
Keyword: 
latticeLWE challengeBDDunique SVPembedding techniqueprogressive BKZ simulatorpost-quantum cryptography
 Summary | Full Text:PDF(1.2MB)

Power of Enumeration — Recent Topics on BDD/ZDD-Based Techniques for Discrete Structure Manipulation
Shin-ichi MINATO 
Publication:   
Publication Date: 2017/08/01
Vol. E100-D  No. 8 ; pp. 1556-1562
Type of Manuscript:  INVITED PAPER (Special Section on Multiple-Valued Logic and VLSI Computing)
Category: 
Keyword: 
BDDZDDdiscrete structuregraph algorithm
 Summary | Full Text:PDF(2.3MB)

Techniques of BDD/ZDD: Brief History and Recent Activity
Shin-ichi MINATO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/07/01
Vol. E96-D  No. 7 ; pp. 1419-1429
Type of Manuscript:  INVITED SURVEY PAPER
Category: 
Keyword: 
BDDZDDdecision diagramdiscrete structurealgorithmdata structure
 Summary | Full Text:PDF(1.2MB)

On Gate Level Power Optimization of Combinational Circuits Using Pseudo Power Gating
Yu JIN Shinji KIMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/12/01
Vol. E95-A  No. 12 ; pp. 2191-2198
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Level Design
Keyword: 
dynamic power reductionswitching activity reductioncontrolling value-based power controllingBDD
 Summary | Full Text:PDF(1.8MB)

Automatic Multi-Stage Clock Gating Optimization Using ILP Formulation
Xin MAN Takashi HORIYAMA Shinji KIMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/08/01
Vol. E95-A  No. 8 ; pp. 1347-1358
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
actual power reductionautomatic multi-stage clock gating optimizationILP formulationswitching activityBDDMIP optimizer
 Summary | Full Text:PDF(2.8MB)

Power Optimization of Sequential Circuits Using Switching Activity Based Clock Gating
Xin MAN Takashi HORIYAMA Shinji KIMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/12/01
Vol. E93-A  No. 12 ; pp. 2472-2480
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
automatic clock gating generationlow powerdynamic power reductionBDD
 Summary | Full Text:PDF(1.3MB)

A Parallel Branching Program Machine for Sequential Circuits: Implementation and Evaluation
Hiroki NAKAHARA Tsutomu SASAO Munehiro MATSUURA Yoshifumi KAWAMURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/08/01
Vol. E93-D  No. 8 ; pp. 2048-2058
Type of Manuscript:  Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing)
Category: Logic Design
Keyword: 
embedded systembranching program machinemulti-processingBDD
 Summary | Full Text:PDF(1MB)

Fine-Grained Power Gating Based on the Controlling Value of Logic Elements
Lei CHEN Takashi HORIYAMA Yuichi NAKAMURA Shinji KIMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/12/01
Vol. E91-A  No. 12 ; pp. 3531-3538
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
power gatingmulti-threshold CMOS (MTCMOS) technologyBDDcontrolling valueleakage power reduction
 Summary | Full Text:PDF(767KB)

Design of Small RSFQ Microprocessor Based on Cell-Based Top-Down Design Methodology
Futabako MATSUZAKI Kenichi YODA Junichi KOSHIYAMA Kei MOTOORI Nobuyuki YOSHIKAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/03/01
Vol. E85-C  No. 3 ; pp. 659-664
Type of Manuscript:  Special Section PAPER (Special Issue on Superconductive Electronics)
Category: Digital Devices and Their Applications
Keyword: 
SFQBDDsuperconducting circuitmicroprocessorstandard cell
 Summary | Full Text:PDF(711.2KB)

Computing the Invariant Polynomials of Graphs, Networks and Matroids
Hiroshi IMAI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2000/03/25
Vol. E83-D  No. 3 ; pp. 330-343
Type of Manuscript:  INVITED SURVEY PAPER
Category: Algorithms for Matroids and Related Discrete Systems
Keyword: 
Tutte polynomialmatroidsimplicial complexnetwork reliabilityBDD
 Summary | Full Text:PDF(513.5KB)

Computational Investigations of All-Terminal Network Reliability via BDDs
Hiroshi IMAI Kyoko SEKINE Keiko IMAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/05/25
Vol. E82-A  No. 5 ; pp. 714-721
Type of Manuscript:  Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
network reliabilityBDDoutput-size sensitive#P-complete
 Summary | Full Text:PDF(586.3KB)

Proposal for Incremental Formal Verification
Toru SHONAI Kazuhiko MATSUMOTO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/11/25
Vol. E81-D  No. 11 ; pp. 1172-1185
Type of Manuscript:  PAPER
Category: Computer Hardware and Design
Keyword: 
formal verificationprocessorpipelineBDDtheorem prover
 Summary | Full Text:PDF(1.1MB)

Single-Electron Logic Systems Based on the Binary Decision Diagram
Noboru ASAHI Masamichi AKAZAWA Yoshihito AMEMIYA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/01/25
Vol. E81-C  No. 1 ; pp. 49-56
Type of Manuscript:  Special Section PAPER (Special Issue on Technology Challenges for Single Electron Devices)
Category: 
Keyword: 
binary decision diagramBDDsingle electronlogic circuitaddercomparator
 Summary | Full Text:PDF(613.4KB)

Counting the Number of Paths in a Graph via BDDs
Kyoko SEKINE Hiroshi IMAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/04/25
Vol. E80-A  No. 4 ; pp. 682-688
Type of Manuscript:  Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
graphspaths#P-completeBDD
 Summary | Full Text:PDF(620.6KB)

A Scheduling Method Using Boolean Equations in High-Level Synthesis
Toshiaki MIYAZAKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/12/25
Vol. E75-A  No. 12 ; pp. 1728-1731
Type of Manuscript:  Special Section LETTER (Special Section on the 1992 IEICE Fall Conference)
Category: 
Keyword: 
integer linear programmingBDDdata path
 Summary | Full Text:PDF(332.3KB)