Keyword : ADPLL


A Fast Settling All Digital PLL Using Temperature Compensated Oscillator Tuning Word Estimation Algorithm
Keisuke OKUNO Shintaro IZUMI Kana MASAKI Hiroshi KAWAGUCHI Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2015/12/01
Vol. E98-A  No. 12 ; pp. 2592-2599
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Circuit Design
Keyword: 
ADPLLfast settlingdigital calibrationtiming error correctiontemperature compensation
 Summary | Full Text:PDF(2.7MB)

Sub-Picosecond Resolution and High-Precision TDC for ADPLLs Using Charge Pump and SAR-ADC
Zule XU Seungjong LEE Masaya MIYAHARA Akira MATSUZAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2015/02/01
Vol. E98-A  No. 2 ; pp. 476-484
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
ADPLLcharge pumpSAR-ADCsub-picosecond resolutionTDCtime-to-charge conversion
 Summary | Full Text:PDF(1.6MB)

Frequency Resolution Enhancement for Digitally-Controlled Oscillator Based on a Single-Period Switching Scheme
Kazutoshi KODAMA Tetsuya IIZUKA Toru NAKURA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/12/01
Vol. E95-C  No. 12 ; pp. 1857-1863
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
DCOADPLLhigh frequency resolution enhancement
 Summary | Full Text:PDF(2.1MB)

A-104 dBc/Hz In-Band Phase Noise 3 GHz All Digital PLL with Phase Interpolation Based Hierarchical Time to Digital Converter
Daisuke MIYASHITA Hiroyuki KOBAYASHI Jun DEGUCHI Shouhei KOUSAI Mototsugu HAMADA Ryuichi FUJIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/06/01
Vol. E95-C  No. 6 ; pp. 1008-1016
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category: 
Keyword: 
ADPLLTDCphase interpolatorphase noise
 Summary | Full Text:PDF(2.8MB)

A Low Jitter ADPLL for Mobile Applications
Kwang-Jin LEE Hyo-Chang KIM Uk-Rae CHO Hyun-Geun BYUN Suki KIM 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/06/01
Vol. E88-C  No. 6 ; pp. 1241-1247
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit and Device Technologies)
Category: PLL
Keyword: 
ADPLLAll Digital PLLDCO
 Summary | Full Text:PDF(1.5MB)