C - Abstracts of IEICE TRANSACTIONS on Electronics (Japanese Edition)

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Online ISSN : 1881-0217
Volume J94-C No.10  (Publication Date:2011/10/01)
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pp.277-287  PAPER
A Solution of Plane Wave Scattering by Doubly Periodic Structures in Three Dimensional Space Using Hybrid Trefftz Finite Elements
Shingo SATO  Koji HASEGAWA  Koichi HIRAYAMA  
Summary | Full Text(in Japanese):PDF (1MB) >>Buy this Article

pp.288-295  PAPER
Estimation of Discharge Currents for Contact Discharges from ESD Gun to Equipment under Test
Fumihiko TOYA  Ikuko MORI  Osamu FUJIWARA  Yoshinori TAKA  Shinobu ISHIGAMI  Yukio YAMANAKA  
Summary | Full Text(in Japanese):PDF (3.5MB) >>Buy this Article

pp.296-305  PAPER
A Broadband Branch-Line Hybrid Utilizing Open-Circuited Interdigital Sections
Takeshi OSHIMA  Takashi YANAGI  Toru FUKASAWA  Hiroaki MIYASHITA  Yoshihiko KONISHI  
Summary | Full Text(in Japanese):PDF (1.3MB) >>Buy this Article

pp.306-315  PAPER
Expansion of Microwave Imaging via Space-Time Beamforming to the Multi-Static Radar for Breast Cancer Detection
Kenta SUZUKI  Hiroyuki HATANO  Yoshihiko KUWAHARA  
Summary | Full Text(in Japanese):PDF (2.2MB) >>Buy this Article

pp.316-322  PAPER
Preparation and Characterization of Thermal Oxidization Anodized Si with a Low-k Dielectric Constant
Tomihiro SONEGAWA  Kazuhiro UEHARA  Takehiro MAEHAMA  
Summary | Full Text(in Japanese):PDF (2.5MB) >>Buy this Article

pp.323-333  PAPER
A Defect Position Identification Method through Dual Channel System for Flat Panel Manufacturing Processes
Hiroshi HAMORI  Masatoshi SAKAWA  Hideki KATAGIRI  Takeshi MATSUI  
Summary | Full Text(in Japanese):PDF (1.6MB) >>Buy this Article

pp.334-335  LETTER
Delta-Sigma Analog-to-Digital Converter with Chaotic Oscillator Using Λ-Type Negative Resistance Device
Katsutoshi SAEKI  Mitsushi NAKAZATO  Yoshifumi SEKINE  
Summary | Full Text(in Japanese):PDF (255.7KB) >>Buy this Article

pp.337-340  LETTER
Phase to Amplitude Converter with Optimized Linear Interpolation and Error Compensation ROM
Taketo NAMBA  Takuya IIDA  Hiroomi HIKAWA  
Summary | Full Text(in Japanese):PDF (566.3KB) >>Buy this Article

pp.341-345  LETTER
Study of Pattern Area Reduction with 3 Dimensional Transistor for Logic Circuit
Yu HIROSHIMA  Takahiro KODAMA  Shigeyoshi WATANABE  
Summary | Full Text(in Japanese):PDF (465.9KB) >>Buy this Article

pp.346-349  LETTER
Study of Pattern Area for Reconfigurable Logic Circuit with DG/CNT Transistor
Takamichi HAYASHI  Shigeyoshi WATANABE  
Summary | Full Text(in Japanese):PDF (826.4KB) >>Buy this Article

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