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C - Abstracts of IEICE TRANSACTIONS on Electronics (Japanese Edition)

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Online ISSN : 1881-0217

Volume J92-C No.11 (Publication Date:2009/11/01)

Special Issue on Advanced Packging and Environmentally Conscious Packaging Technologies in Next-Generation Electronic Equipment

pp.581-594 PAPER Future Direction of Solid State Micro-Joining Applied to Environmentally Friendly Electronic Packaging Yasuo TAKAHASHI
	Summary \| Full Text(in Japanese):PDF (3.1MB)

pp.595-605 PAPER Trends and Future Technology Direction of Wafer Level Chip Scale Packages Hiroshi YAMADA
	Summary \| Full Text(in Japanese):PDF (2.1MB)

pp.606-612 PAPER Consideration of Tin Whisker Growth Mechanism for Lead-Free Plating Seiki SAKUYAMA Michinori KUTAMI
	Summary \| Full Text(in Japanese):PDF (1.1MB)

pp.613-621 PAPER Mechanical Reliability of Cu/low-k On-Chip Interconnect in FCBGA Chihiro J. UCHIBORI Michael LEE Xeufeng ZANG Paul S. HO
	Summary \| Full Text(in Japanese):PDF (1.3MB)

pp.622-631 PAPER Health-Monitoring for Electronic Assembly Board of Digital Products -- Monitoring Method for Assessment of Field Load and Thermal Performance Degradation -- Kenji HIROHATA Katsumi HISANO Minoru MUKAI
	Summary \| Full Text(in Japanese):PDF (1.8MB)

pp.632-639 PAPER Bonding Technology of Micro-Components on Wafer for MEMS Device of Layer Stack Structure Using Manipulator Hiroyuki MOTOHARA Mikio NAKAMURA
	Summary \| Full Text(in Japanese):PDF (1.1MB)

pp.640-645 PAPER Properties of Insulator Using O₃-TEOS CVD for MEMS TSV Electrodes Akinobu KANAI Makoto MORIGUCHI Sho SASAKI Masatoshi OBA
	Summary \| Full Text(in Japanese):PDF (535.5KB)

pp.646-654 PAPER Practical Use of 3D Stacking Technology Using Direct Connection between TSV and Bump Nobuaki MIYAKAWA Eiri HASHIMOTO Takanori MAEBASHI Natsuo NAKAMURA Yutaka SACHO Shigeto NAKAYAMA Shinjiro TOYODA
	Summary \| Full Text(in Japanese):PDF (7.8MB)

pp.655-663 PAPER Embedded Decoupling Capacitors Technology for Si Interposer Applications Takeshi SHIOGA John D. BANIECKI Masatoshi ISHII Kazuaki KURIHARA Yoshikatsu ISHIZUKI Masataka MIZUKOSHI
	Summary \| Full Text(in Japanese):PDF (1.6MB)

pp.664-670 PAPER IC Embedded Polyimide Multilayer Wiring Boards Utilizing Wafer Level Packaging Technology Satoshi OKUDE Masahiro OKAMOTO Takanao SUZUKI Osamu NAKAO
	Summary \| Full Text(in Japanese):PDF (1.5MB)

pp.671-679 PAPER Wafer Level CSP Technology and Application to Embedded Inductor Yutaka AOKI Osamu OKADA Osamu KUWABARA Tomoyuki KOSUGI Syoichi KOTANI Kazuhiro MASUDA Ichiro MIHARA Takeshi WAKABAYASHI
	Summary \| Full Text(in Japanese):PDF (2MB)

pp.680-687 PAPER Semiconductor Package for 43 Gbit/s Transmission with Thin Transmission Line Lead Hiroshi KIKUCHI Norio NAKAZATO Naotaka TANAKA Satoru ISOMURA
	Summary \| Full Text(in Japanese):PDF (1.6MB)

pp.688-694 PAPER Basic Study on System Design Method for Proper System LSI Packaging in Mobile Phone Yoshiharu IWATA Atsushi TAYA Ryohei SATOH Kazuya OKAMOTO Keiji KUDO
	Summary \| Full Text(in Japanese):PDF (1.1MB)

pp.695-702 PAPER Design Solution Improvement for Electrical-Thermal Collaborated Design by Using Multi-Agent Theory -- Outline Layout Design Automation by Collaboration between Thermal Layout and Circuit Layout -- Yoshiharu IWATA Shintaro HAYASHI Ryohei SATOH Kozo FUJIMOTO
	Summary \| Full Text(in Japanese):PDF (789.7KB)

pp.703-711 PAPER Development of Full-Stacked Via Printed Wiring Board with High Thermal Reliability Akihiko HAPPOYA Akira TANAKA Kenji HIROHATA Shun OKAYAMA
	Summary \| Full Text(in Japanese):PDF (1.7MB)

pp.712-721 PAPER Burn-In Test Chip-Carrier for LSI Chips with Micro Pad Pitch Motohiro SUZUKI Tokihiko YOKOSHIMA Yoshikuni OKADA Hiroshi NAKAGAWA Masahiro AOYAGI Masatoshi MIURA Tsuyoshi TAKAHASHI Kimiya KITAYAMA Atsushi ETOU Tomohiro HIMENO Akira MARUI
	Summary \| Full Text(in Japanese):PDF (1.5MB)

Regular Section

pp.722-730 PAPER Design of Thermo-Tunable Couplers Based on Solid-Core Photonic Band-Gap Fibers Ryuichi YOSHIDA Yukihiro TSUCHIDA Tadashi MURAO Kunimasa SAITOH Masanori KOSHIBA
	Summary \| Full Text(in Japanese):PDF (1.8MB)

pp.731-741 PAPER Analysis of Stripline Right-Angle Bend with Square-Shaped Corner Cut and Discussion on the Optimum Cut Based on Planar Circuit Model and Foster-Type Equivalent Network Takaharu HIRAOKA Jui-pang HSU
	Summary \| Full Text(in Japanese):PDF (1.8MB)

pp.742-743 LETTER Proposal of a FinFET Type DTMOS Yu HIROSHIMA Shigeyoshi WATANABE
	Summary \| Full Text(in Japanese):PDF (261.2KB)

pp.745-749 LETTER Phase Noise Estimation for the ORIGAMI Oscillator Takeshi SHIMA Takashi KUSAGA
	Summary \| Full Text(in Japanese):PDF (269.5KB)