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Online ISSN : 1745-1353

Volume E99-C No.8 (Publication Date:2016/08/01)
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Special Section on Low-Power and High-Speed Chips

pp.899-900 FOREWORD Open Access Paper FOREWORD Fumio ARAKAWA Makoto IKEDA
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pp.901-908 PAPER A 28-nm 484-fJ/writecycle 650-fJ/readcycle 8T Three-Port FD-SOI SRAM for Image Processor Haruki MORI Yohei UMEKI Shusuke YOSHIMOTO Shintaro IZUMI Koji NII Hiroshi KAWAGUCHI Masahiko YOSHIMOTO
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pp.909-917 PAPER Multi-Voltage Variable Pipeline Routers with the Same Clock Frequency for Low-Power Network-on-Chips Systems Akram BEN AHMED Hiroki MATSUTANI Michihiro KOIBUCHI Kimiyoshi USAMI Hideharu AMANO
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pp.918-925 PAPER A Slack Reclamation Method for Reducing the Speed Fluctuations on the DVFS Real-Time Scheduling Da-Ren CHEN Chiun-Chieh HSU Hon-Chan CHEN
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pp.926-935 PAPER An Operating System Guided Fine-Grained Power Gating Control Based on Runtime Characteristics of Applications Atsushi KOSHIBA Mikiko SATO Kimiyoshi USAMI Hideharu AMANO Ryuichi SAKAMOTO Masaaki KONDO Hiroshi NAKAMURA Mitaro NAMIKI
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pp.936-946 PAPER Improvement of Data Utilization Efficiency for Cache Memory by Compressing Frequent Bit Sequences Ryotaro KOBAYASHI Ikumi KANEKO Hajime SHIMADA
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Regular Section

pp.947-955 PAPER-Electromagnetic Theory New Estimation Method for the Operational Low Frequency End of Antipodal Vivaldi Antennas Hien Ba CHU Hiroshi SHIRAI Chien Dao NGOC
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pp.956-962 PAPER-Electronic Circuits A Short-Time Three-Phase Single-Rail Precharge Logic against Differential Power Analysis Wenyi TANG Song JIA Yuan WANG
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pp.963-973 PAPER-Electronic Circuits A 9.35-ENOB, 14.8 fJ/conv.-step Fully-Passive Noise-Shaping SAR ADC Zhijie CHEN Masaya MIYAHARA Akira MATSUZAWA
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pp.974-983 PAPER-Electronic Circuits Low Power High Performance FinFET Standard Cells Based on Mixed Back Biasing Technology Tian WANG Xiaoxin CUI Kai LIAO Nan LIAO Xiaole CUI Dunshan YU
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