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Online ISSN : 1745-1353

Volume E95-C No.4 (Publication Date:2012/04/01)

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Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology

pp.413-413 FOREWORD FOREWORD Masahiko YOSHIMOTO
	Summary \| Full Text:PDF (95.2KB)

pp.414-420 PAPER-INVITED Impact of Discrete-Charge-Induced Variability on Scaled MOS Devices Kiyoshi TAKEUCHI
	Summary \| Full Text:PDF (925KB)

pp.421-431 PAPER-INVITED Digital Calibration and Correction Methods for CMOS Analog-to-Digital Converters Shiro DOSHO
	Summary \| Full Text:PDF (1.8MB)

pp.432-440 PAPER An H.264/AVC High422 Profile and MPEG-2 422 Profile Encoder LSI for HDTV Broadcasting Infrastructures Koyo NITTA Hiroe IWASAKI Takayuki ONISHI Takashi SANO Atsushi SAGATA Yasuyuki NAKAJIMA Minoru INAMORI Ryuichi TANIDA Atsushi SHIMIZU Ken NAKAMURA Mitsuo IKEDA Jiro NAGANUMA
	Summary \| Full Text:PDF (4.1MB)

pp.441-446 PAPER A 64 Cycles/MB, Luma-Chroma Parallelized H.264/AVC Deblocking Filter for 4 K2 K Applications Weiwei SHEN Yibo FAN Xiaoyang ZENG
	Summary \| Full Text:PDF (1.8MB)

pp.447-455 PAPER An 88/44 Adaptive Hadamard Transform Based FME VLSI Architecture for 4 K2 K H.264/AVC Encoder Yibo FAN Jialiang LIU Dexue ZHANG Xiaoyang ZENG Xinhua CHEN
	Summary \| Full Text:PDF (2.1MB)

pp.456-467 PAPER A VLSI Architecture with Multiple Fast Store-Based Block Parallel Processing for Output Probability and Likelihood Score Computations in HMM-Based Isolated Word Recognition Kazuhiro NAKAMURA Ryo SHIMAZAKI Masatoshi YAMAMOTO Kazuyoshi TAKAGI Naofumi TAKAGI
	Summary \| Full Text:PDF (2.3MB)

pp.468-477 PAPER High Uniqueness Arbiter-Based PUF Circuit Utilizing RG-DTM Scheme for Identification and Authentication Applications Mitsuru SHIOZAKI Kota FURUHASHI Takahiko MURAYAMA Akitaka FUKUSHIMA Masaya YOSHIKAWA Takeshi FUJINO
	Summary \| Full Text:PDF (2.2MB)

pp.478-486 PAPER An Area-Efficient Reconfigurable LDPC Decoder with Conflict Resolution Changsheng ZHOU Yuebin HUANG Shuangqu HUANG Yun CHEN Xiaoyang ZENG
	Summary \| Full Text:PDF (1.8MB)

pp.487-494 PAPER A Small-Area and Low-Power SoC for Less-Invasive Pressure Sensing Capsules in Ambulatory Urodynamic Monitoring Hirofumi IWATO Keishi SAKANUSHI Yoshinori TAKEUCHI Masaharu IMAI
	Summary \| Full Text:PDF (1.3MB)

pp.495-505 PAPER Hybrid Wired/Wireless On-Chip Network Design for Application-Specific SoC Shouyi YIN Yang HU Zhen ZHANG Leibo LIU Shaojun WEI
	Summary \| Full Text:PDF (718.2KB)

pp.506-515 PAPER Integration of Behavioral Synthesis and Floorplanning for Asynchronous Circuits with Bundled-Data Implementation Naohiro HAMADA Hiroshi SAITO
	Summary \| Full Text:PDF (995.7KB)

pp.516-522 PAPER Asynchronous Circuit Design on Field Programmable Gate Array Devices Jung-Lin YANG Shin-Nung LU Pei-Hsuan YU
	Summary \| Full Text:PDF (921.6KB)

pp.523-533 PAPER A Process-Variation-Adaptive Network-on-Chip with Variable-Cycle Routers and Variable-Cycle Pipeline Adaptive Routing Yohei NAKATA Hiroshi KAWAGUCHI Masahiko YOSHIMOTO
	Summary \| Full Text:PDF (2.2MB)

pp.534-545 PAPER Cluster Generation and Network Component Insertion for Topology Synthesis of Application-Specific Network-on-Chips Wei ZHONG Takeshi YOSHIMURA Bei YU Song CHEN Sheqin DONG Satoshi GOTO
	Summary \| Full Text:PDF (2MB)

pp.546-554 PAPER Energy Minimum Operation with Self Synchronous Gate-Level Autonomous Power Gating and Voltage Scaling Benjamin DEVLIN Makoto IKEDA Kunihiro ASADA
	Summary \| Full Text:PDF (4.2MB)

pp.555-563 PAPER 0.5-V 25-nm 6-T Cell with Boosted Word Voltage for 1-Gb SRAMs Akira KOTABE Kiyoo ITOH Riichiro TAKEMURA
	Summary \| Full Text:PDF (1.8MB)

pp.564-571 PAPER Analysis of Operation Margin and Read Speed in 6T- and 8T-SRAM with Local Electron Injected Asymmetric Pass Gate Transistor Kousuke MIYAJI Kentaro HONDA Shuhei TANAKAMARU Shinji MIYANO Ken TAKEUCHI
	Summary \| Full Text:PDF (4.5MB)

pp.572-578 PAPER A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM Using Low-Energy Disturb Mitigation Scheme Shusuke YOSHIMOTO Masaharu TERADA Shunsuke OKUMURA Toshikazu SUZUKI Shinji MIYANO Hiroshi KAWAGUCHI Masahiko YOSHIMOTO
	Summary \| Full Text:PDF (1.9MB)

pp.579-585 PAPER A 0.15-µm FD-SOI Substrate Bias Control SRAM with Inter-Die Variability Compensation Scheme Shunsuke OKUMURA Hidehiro FUJIWARA Kosuke YAMAGUCHI Shusuke YOSHIMOTO Masahiko YOSHIMOTO Hiroshi KAWAGUCHI
	Summary \| Full Text:PDF (1.8MB)

pp.586-593 PAPER Evaluation of SRAM-Core Susceptibility against Power Supply Voltage Variation Takuya SAWADA Taku TOSHIKAWA Kumpei YOSHIKAWA Hidehiro TAKATA Koji NII Makoto NAGATA
	Summary \| Full Text:PDF (3MB)

pp.594-599 PAPER Small-Sized Leakage-Controlled Gated Sense Amplifier for 0.5-V Multi-Gigabit DRAM Arrays Akira KOTABE Riichiro TAKEMURA Yoshimitsu YANAGAWA Tomonori SEKIGUCHI Kiyoo ITOH
	Summary \| Full Text:PDF (2.3MB)

pp.600-608 PAPER A Low-V_t Small-Offset Gated-Preamplifier for Sub-1-V DRAM Mid-Point Sensing Satoru AKIYAMA Riichiro TAKEMURA Tomonori SEKIGUCHI Akira KOTABE Kiyoo ITOH
	Summary \| Full Text:PDF (2MB)

pp.609-616 PAPER Initialize and Weak-Program Erasing Scheme for High-Performance and High-Reliability Ferroelectric NAND Flash Solid-State Drive Kousuke MIYAJI Ryoji YAJIMA Teruyoshi HATANAKA Mitsue TAKAHASHI Shigeki SAKAI Ken TAKEUCHI
	Summary \| Full Text:PDF (1.8MB)

pp.617-626 PAPER Current Controlled MOS Current Mode Logic with Auto-Detection of Threshold Voltage Fluctuation Hyoungjun NA Tetsuo ENDOH
	Summary \| Full Text:PDF (1.9MB)

pp.627-634 PAPER All-Digital PMOS and NMOS Process Variability Monitor Utilizing Shared Buffer Ring and Ring Oscillator Tetsuya IIZUKA Kunihiro ASADA
	Summary \| Full Text:PDF (2.2MB)

pp.635-642 PAPER 3-D Range Map Acquisition System Based on CMOS Image Sensor Using Time-Multiplexing Structured Pattern Hiroki YABE Makoto IKEDA
	Summary \| Full Text:PDF (2.4MB)

pp.643-650 PAPER On-Chip Switched Parasitic Capacitors of Sleep Blocks for Resonant Supply Noise Reduction Jinmyoung KIM Toru NAKURA Hidehiro TAKATA Koichiro ISHIBASHI Makoto IKEDA Kunihiro ASADA
	Summary \| Full Text:PDF (2.3MB)

pp.651-660 PAPER Fluctuation Tolerant Charge-Integration Read Scheme for Ultrafast DNA Sequencing with Nanopore Device Kazuo ONO Yoshimitsu YANAGAWA Akira KOTABE Riichiro TAKEMURA Tatsuo NAKAGAWA Tomio IWASAKI Takayuki KAWAHARA
	Summary \| Full Text:PDF (3.5MB)

pp.661-667 PAPER A 580 fs-Resolution Time-to-Digital Converter Utilizing Differential Pulse-Shrinking Buffer Ring in 0.18 µm CMOS Technology Tetsuya IIZUKA Satoshi MIURA Ryota YAMAMOTO Yutaka CHIBA Shunichi KUBO Kunihiro ASADA
	Summary \| Full Text:PDF (4MB)

pp.668-676 PAPER 6 W/25 mm² Wireless Power Transmission for Non-contact Wafer-Level Testing Andrzej RADECKI Hayun CHUNG Yoichi YOSHIDA Noriyuki MIURA Tsunaaki SHIDEI Hiroki ISHIKURO Tadahiro KURODA
	Summary \| Full Text:PDF (4.3MB)

pp.677-685 PAPER A Current-Mode Buck DC-DC Converter with Frequency Characteristics Independent of Input and Output Voltages Using a Quadratic Compensation Slope Toru SAI Yasuhiro SUGIMOTO
	Summary \| Full Text:PDF (2MB)

pp.686-695 PAPER A 0.7-V Opamp in Scaled Low-Standby-Power FinFET Technology Shin-ichi O'UCHI Kazuhiko ENDO Takashi MATSUKAWA Yongxun LIU Tadashi NAKAGAWA Yuki ISHIKAWA Junichi TSUKADA Hiromi YAMAUCHI Toshihiro SEKIGAWA Hanpei KOIKE Kunihiro SAKAMOTO Meishoku MASAHARA
	Summary \| Full Text:PDF (3.9MB)

pp.696-705 PAPER Layout-Aware Variability Characterization of CMOS Current Sources Bo LIU Bo YANG Shigetoshi NAKATAKE
	Summary \| Full Text:PDF (1.9MB)

pp.706-709 BRIEF PAPER Ultra High Speed Modified Booth Encoding Architecture for High Speed Parallel Accumulations Amir FATHI Sarkis AZIZIAN Khayrollah HADIDI Abdollah KHOEI
	Summary \| Full Text:PDF (271.5KB)

pp.710-712 BRIEF PAPER A Novel and Very Fast 4-2 Compressor for High Speed Arithmetic Operations Amir FATHI Sarkis AZIZIAN Khayrollah HADIDI Abdollah KHOEI
	Summary \| Full Text:PDF (488.1KB)

pp.713-716 BRIEF PAPER Third-Harmonic Envelope Feedback Method for High-Efficiency Linear Power Amplifiers Shoichi OSHIMA Mamoru UGAJIN Mitsuru HARADA
	Summary \| Full Text:PDF (685.5KB)

Regular Section

pp.717-724 PAPER-Electromagnetic Theory Estimation of Surface Waves along a Metal Grating Using an Equivalent Impedance Model Michinari SHIMODA Toyonori MATSUDA Kazunori MATSUO Yoshitada IYAMA
	Summary \| Full Text:PDF (814.8KB)

pp.725-732 PAPER-Electromagnetic Theory Frequency-Dependent Formulations of a Drude-Critical Points Model for Explicit and Implicit FDTD Methods Using the Trapezoidal RC Technique Jun SHIBAYAMA Keisuke WATANABE Ryoji ANDO Junji YAMAUCHI Hisamatsu NAKANO
	Summary \| Full Text:PDF (1.6MB)

pp.733-743 PAPER-Electronic Circuits An Ultra-Low Voltage Analog Front End for Strain Gauge Sensory System Application in 0.18 µm CMOS Alexander EDWARD Pak Kwong CHAN
	Summary \| Full Text:PDF (1.2MB)

pp.744-751 PAPER-Electronic Circuits An Energy-Efficient Full Adder Cell Using CNFET Technology Mohammad Reza RESHADINEZHAD Mohammad Hossein MOAIYERI Kaivan NAVI
	Summary \| Full Text:PDF (1.2MB)

pp.752-760 PAPER-Semiconductor Materials and Devices High-Frequency Precise Characterization of Intrinsic FinFET Channel Hideo SAKAI Shinichi O'UCHI Takashi MATSUKAWA Kazuhiko ENDO Yongxun LIU Junichi TSUKADA Yuki ISHIKAWA Tadashi NAKAGAWA Toshihiro SEKIGAWA Hanpei KOIKE Kunihiro SAKAMOTO Meishoku MASAHARA Hiroki ISHIKURO
	Summary \| Full Text:PDF (2.2MB)

pp.761-764 BRIEF PAPER-Optoelectronics Transverse Characteristics of Two-Dimensional Imaging by Fourier Domain Optical Coherence Tomography Yu SUGITA Yoshifumi TAKASAKI Keiji KURODA Yuzo YOSHIKUNI
	Summary \| Full Text:PDF (271.9KB)

pp.765-767 BRIEF PAPER-Electronic Circuits A New Common-Mode Stabilization Method for a CMOS Cascode Class-E Power Amplifier with Driver Stage Zhisheng LI Johan BAUWELINCK Guy TORFS Xin YIN Jan VANDEWEGE
	Summary \| Full Text:PDF (218KB)