IEICE TRANSACTIONS on Electronics

Archive Index

Online ISSN : 1745-1353
Volume E91-C No.4  (Publication Date:2008/04/01)
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Special Section on Advanced Technologies in Digital LSIs and Memories

pp.399-399  FOREWORD
FOREWORD
Masao NAKAYA  
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pp.400-409  PAPER
A Low-Power Instruction Issue Queue for Microprocessors
Shingo WATANABE  Akihiro CHIYONOBU  Toshinori SATO  
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pp.410-417  PAPER
Reliable Cache Architectures and Task Scheduling for Multiprocessor Systems
Makoto SUGIHARA  Tohru ISHIHARA  Kazuaki MURAKAMI  
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pp.418-431  PAPER
Temperature-Aware Configurable Cache to Reduce Energy in Embedded Systems
Hamid NOORI  Maziar GOUDARZI  Koji INOUE  Kazuaki MURAKAMI  
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pp.432-439  PAPER
Power-Aware Compiler Controllable Chip Multiprocessor
Hiroaki SHIKANO  Jun SHIRAKO  Yasutaka WADA  Keiji KIMURA  Hironori KASAHARA  
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pp.440-448  PAPER
Reconfigurable Variable Block Size Motion Estimation Architecture for Search Range Reduction Algorithm
Yibo FAN  Takeshi IKENAGA  Satoshi GOTO  
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pp.449-456  PAPER
A 41 mW VGA@30 fps Quadtree Video Encoder for Video Surveillance Systems
Qin LIU  Seiichiro HIRATSUKA  Kazunori SHIMIZU  Shinsuke USHIKI  Satoshi GOTO  Takeshi IKENAGA  
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pp.457-464  PAPER
A VGA 30-fps Realtime Optical-Flow Processor Core for Moving Picture Recognition
Yuichiro MURACHI  Yuki FUKUYAMA  Ryo YAMAMOTO  Junichi MIYAKOSHI  Hiroshi KAWAGUCHI  Hajime ISHIHARA  Masayuki MIYAMA  Yoshio MATSUDA  Masahiko YOSHIMOTO  
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pp.465-478  PAPER
A Sub 100 mW H.264 MP@L4.1 Integer-Pel Motion Estimation Processor Core for MBAFF Encoding with Reconfigurable Ring-Connected Systolic Array and Segmentation-Free, Rectangle-Access Search-Window Buffer
Yuichiro MURACHI  Junichi MIYAKOSHI  Masaki HAMAMOTO  Takahiro IINUMA  Tomokazu ISHIHARA  Fang YIN  Jangchung LEE  Hiroshi KAWAGUCHI  Masahiko YOSHIMOTO  
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pp.479-486  PAPER
Design of a Trinocular-Stereo-Vision VLSI Processor Based on Optimal Scheduling
Masanori HARIYAMA  Naoto YOKOYAMA  Michitaka KAMEYAMA  
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pp.487-496  PAPER
Automatic Synthesis of Cost Effective FFT/IFFT Cores for VLSI OFDM Systems
Nicola E. L'INSALATA  Sergio SAPONARA  Luca FANUCCI  Pierangelo TERRENI  
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pp.497-508  PAPER
A Reconfigurable Functional Unit with Conditional Execution for Multi-Exit Custom Instructions
Hamid NOORI  Farhad MEHDIPOUR  Koji INOUE  Kazuaki MURAKAMI  
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pp.509-516  PAPER
Regular Fabric of Via Programmable Logic Device Using EXclusive-or Array (VPEX) for EB Direct Writing
Akihiro NAKAMURA  Masahide KAWARASAKI  Kouta ISHIBASHI  Masaya YOSHIKAWA  Takeshi FUJINO  
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pp.517-525  PAPER
Multi-Context FPGA Using Fine-Grained Interconnection Blocks and Its CAD Environment
Hasitha Muthumala WAIDYASOORIYA  Weisheng CHONG  Masanori HARIYAMA  Michitaka KAMEYAMA  
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pp.526-533  PAPER
A Design of Constant-Charge-Injection Programming Scheme for AG-AND Flash Memories Using Array-Level Analytical Model
Shinya KAJIYAMA  Ken'ichiro SONODA  Kazuo OTSUGA  Hideaki KURATA  Kiyoshi ISHIKAWA  
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pp.534-542  PAPER
FinFET-Based Flex-Vth SRAM Design for Drastic Standby-Leakage-Current Reduction
Shin-ichi O'UCHI  Meishoku MASAHARA  Kazuhiko ENDO  Yongxun LIU  Takashi MATSUKAWA  Kunihiro SAKAMOTO  Toshihiro SEKIGAWA  Hanpei KOIKE  Eiichi SUZUKI  
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pp.543-552  PAPER
A 10T Non-precharge Two-Port SRAM Reducing Readout Power for Video Processing
Hiroki NOGUCHI  Yusuke IGUCHI  Hidehiro FUJIWARA  Shunsuke OKUMURA  Yasuhiro MORITA  Koji NII  Hiroshi KAWAGUCHI  Masahiko YOSHIMOTO  
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pp.553-561  PAPER
Clock Driver Design for Low-Power High-Speed 90-nm CMOS Register Array
Tadayoshi ENOMOTO  Suguru NAGAYAMA  Hiroaki SHIKANO  Yousuke HAGIWARA  
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pp.562-570  PAPER
Statistical Corner Conditions of Interconnect Delay (Corner LPE Specifications)
Kenta YAMADA  Noriaki ODA  
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pp.571-580  PAPER
Redundant Vias Insertion for Performance Enhancement in 3D ICs
Xu ZHANG  Xiaohong JIANG  Susumu HORIGUCHI  
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pp.581-588  PAPER
Power-Aware Asynchronous Peer-to-Peer Duplex Communication System Based on Multiple-Valued One-Phase Signaling
Kazuyasu MIZUSAWA  Naoya ONIZAWA  Takahiro HANYU  
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pp.589-594  PAPER
Highly Reliable Multiple-Valued Current-Mode Comparator Based on Active-Load Dual-Rail Operation
Masatomo MIURA  Takahiro HANYU  
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Regular Section

pp.595-606  PAPER-Electromagnetic Theory
Co-modeling, Experimental Verification, and Analysis of Chip-Package Hierarchical Power Distribution Network
Hyunjeong PARK  Hyungsoo KIM  Jun So PAK  Changwook YOON  Kyoungchoul KOO  Joungho KIM  
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pp.607-614  PAPER-Electromagnetic Theory
TM Plane Wave Reflection and Transmission from a One-Dimensional Random Slab
Yasuhiko TAMURA  
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pp.615-624  PAPER-Electromagnetic Theory
Design Method for a Low-Profile Dual-Shaped Reflector Antenna with an Elliptical Aperture by the Suppression of Undesired Scattering
Yoshio INASAWA  Shinji KURODA  Kenji KUSAKABE  Izuru NAITO  Yoshihiko KONISHI  Shigeru MAKINO  Makio TSUCHIYA  
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pp.625-630  PAPER-Electromagnetic Theory
Planar T-Shaped Monopole Antenna for WLAN/WiMAX Applications
Jhin-Fang HUANG  Shih-Huang WU  
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pp.631-637  PAPER-Electromagnetic Theory
Characterization of Two-Stage Composite Right- and Left-Handed Transmission Lines
Shun NAKAGAWA  Koichi NARAHARA  
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pp.638-646  PAPER-Microwaves, Millimeter-Waves
Computer Simulation about Temperature Distribution of an EM-Wave Absorber Using a Coupled Analysis Method
Shinya WATANABE  Akitoshi TANIGUCHI  Kota SAITO  Osamu HASHIMOTO  Toshifumi SAITO  Hiroshi KURIHARA  
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pp.647-654  PAPER-Semiconductor Materials and Devices
Concise Modeling of Transistor Variations in an LSI Chip and Its Application to SRAM Cell Sensitivity Analysis
Masakazu AOKI  Shin-ichi OHKAWA  Hiroo MASUDA  
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pp.655-661  PAPER-Integrated Electronics
A PVT Tolerant STM-16 Clock-and-Data Recovery LSI Using an On-Chip Loop-Gain Variation Compensation Architecture in 0.20-µm CMOS/SOI
Yusuke OHTOMO  Hiroshi KOIZUMI  Kazuyoshi NISHIMURA  Masafumi NOGAWA  
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pp.662-665  LETTER-Electronic Circuits
An Ultra-Low-Voltage Ultra-Low-Power Weak Inversion Composite MOS Transistor: Concept and Applications
Luis H.C. FERREIRA  Tales C. PIMENTA  Robson L. MORENO  
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pp.666-669  LETTER-Electronic Circuits
High-Input and Low-Output Impedance Voltage-Mode Universal DDCC and FDCCII Filter
Hua-Pin CHEN  Wan-Shing YANG  
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pp.670-672  LETTER-Semiconductor Materials and Devices
A Low-Cost BIST Based on Histogram Testing for Analog to Digital Converters
Kicheol KIM  Youbean KIM  Incheol KIM  Hyeonuk SON  Sungho KANG  
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