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Online ISSN : 1745-1353

Volume E90-C No.4 (Publication Date:2007/04/01)

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Special Section on Low-Power, High-Speed LSIs and Related Technologies

pp.655-656 FOREWORD FOREWORD Tadahiro KURODA
	Summary \| Full Text:PDF (55.7KB) \| Errata(VOL.E90-C,NO.5,2007)

pp.657-665 PAPER-INVITED Continuous Design Efforts for Ubiquitous Network Era under the Physical Limitation of Advanced CMOS Kazutami ARIMOTO Toshihiro HATTORI Hidehiro TAKATA Atsushi HASEGAWA Toru SHIMIZU
	Summary \| Full Text:PDF (1.8MB)

pp.666-674 PAPER-Digital Boosted Voltage Scheme with Active Body-Biasing Control on PD-SOI for Ultra Low Voltage Operation Masaaki IIJIMA Masayuki KITAMURA Masahiro NUMA Akira TADA Takashi IPPOSHI Shigeto MAEGAWA
	Summary \| Full Text:PDF (863KB)

pp.675-682 PAPER-Digital Asymmetric Slope Dual Mode Differential Logic Circuit for Compatibility of Low-Power and High-Speed Operations Masao MORIMOTO Makoto NAGATA Kazuo TAKI
	Summary \| Full Text:PDF (567.8KB)

pp.683-691 PAPER-Digital Design and Evaluation of a 5454-bit Multiplier Based on Differential-Pair Circuitry Akira MOCHIZUKI Hirokatsu SHIRAHAMA Takahiro HANYU
	Summary \| Full Text:PDF (1.5MB)

pp.692-698 PAPER-Digital Substrate-Noise and Random-Variability Reduction with Self-Adjusted Forward Body Bias Yoshihide KOMATSU Koichiro ISHIBASHI Makoto NAGATA
	Summary \| Full Text:PDF (2.2MB)

pp.699-707 PAPER-Digital A 90 nm LUT Array for Speed and Yield Enhancement by Utilizing Within-Die Delay Variations Kazuya KATSUKI Manabu KOTANI Kazutoshi KOBAYASHI Hidetoshi ONODERA
	Summary \| Full Text:PDF (664.2KB)

pp.708-717 PAPER-Digital Cooperative Cache System: A Low Power Cache System for Embedded Processors Gi-Ho PARK Kil-Whan LEE Tack-Don HAN Shin-Dug KIM
	Summary \| Full Text:PDF (1.2MB)

pp.718-726 PAPER-Digital A Multiple Block-matching Step (MBS) Algorithm for H.26x/MPEG4 Motion Estimation and a Low-Power CMOS Absolute Differential Accumulator Circuit Tadayoshi ENOMOTO Nobuaki KOBAYASHI Tomomi EI
	Summary \| Full Text:PDF (1.9MB)

pp.727-730 LETTER-Digital The Front-End LSI with a 5-Tap PRML for 2 Reading and Writing of BD-R/RW/ROM GoangSeog CHOI JumHan BAE HyunSoo PARK
	Summary \| Full Text:PDF (653.8KB)

pp.731-734 LETTER-Digital A Novel Low-Power Bus Design for Bus-Invert Coding Myungchul YOON Byeong-hee ROH
	Summary \| Full Text:PDF (367.7KB)

pp.735-742 PAPER-INVITED Low-Voltage Embedded RAMs in Nanometer Era Takayuki KAWAHARA
	Summary \| Full Text:PDF (1.1MB)

pp.743-748 PAPER-Memory A Self-Alignment Row-by-Row Variable-V_DD Scheme Reducing 90% of Active-Leakage Power in SRAM's Fayez Robert SALIBA Hiroshi KAWAGUCHI Takayasu SAKURAI
	Summary \| Full Text:PDF (994.7KB)

pp.749-757 PAPER-Memory A 1R/1W SRAM Cell Design to Keep Cell Current and Area Saving against Simultaneous Read/Write Disturbed Accesses Hiroyuki YAMAUCHI Toshikazu SUZUKI Yoshinobu YAMAGAMI
	Summary \| Full Text:PDF (1.2MB)

pp.758-764 PAPER-Memory Long-Retention-Time, High-Speed DRAM Array with 12-F² Twin Cell for Sub 1-V Operation Riichiro TAKEMURA Kiyoo ITOH Tomonori SEKIGUCHI Satoru AKIYAMA Satoru HANZAWA Kazuhiko KAJIGAYA Takayuki KAWAHARA
	Summary \| Full Text:PDF (1.6MB)

pp.765-771 PAPER-Memory A Capacitorless Twin-Transistor Random Access Memory (TTRAM) on SOI Fukashi MORISHITA Hideyuki NODA Isamu HAYASHI Takayuki GYOHTEN Mako OKAMOTO Takashi IPPOSHI Shigeto MAEGAWA Katsumi DOSAKA Kazutami ARIMOTO
	Summary \| Full Text:PDF (933KB)

pp.772-778 PAPER-Memory Selective-Capacitance Constant-Charge-Injection Programming Scheme for High-Speed Multilevel AG-AND Flash Memories Kazuo OTSUGA Hideaki KURATA Satoshi NODA Yoshitaka SASAGO Tsuyoshi ARIGANE Tetsufumi KAWAMURA Takashi KOBAYASHI
	Summary \| Full Text:PDF (1000.5KB)

pp.779-785 PAPER-INVITED Design Challenges of Analog-to-Digital Converters in Nanoscale CMOS Akira MATSUZAWA
	Summary \| Full Text:PDF (706.3KB)

pp.786-792 PAPER-Analog and Communications An Outside-Rail Opamp Design Relaxing Low-Voltage Constraint on Future Scaled Transistors Koichi ISHIDA Atit TAMTRAKARN Hiroki ISHIKURO Makoto TAKAMIYA Takayasu SAKURAI
	Summary \| Full Text:PDF (760.6KB)

pp.793-801 PAPER-Analog and Communications Analysis and Design of Direct Reference Feed-Forward Compensation for Fast-Settling All-Digital Phase-Locked Loop Win CHAIVIPAS Akira MATSUZAWA
	Summary \| Full Text:PDF (1004.7KB)

pp.802-810 PAPER-Analog and Communications A Multi-Band Burst-Mode Clock and Data Recovery Circuit Che-Fu LIANG Sy-Chyuan HWU Shen-Iuan LIU
	Summary \| Full Text:PDF (2.4MB)

pp.811-822 PAPER-Analog and Communications 18-GHz Clock Distribution Using a Coupled VCO Array Takayuki SHIBASAKI Hirotaka TAMURA Kouichi KANDA Hisakatsu YAMAGUCHI Junji OGAWA Tadahiro KURODA
	Summary \| Full Text:PDF (2.2MB)

pp.823-828 PAPER-Analog and Communications An Integrated Low-Power CMOS Up-Conversion Mixer Using New Stacked Marchand Baluns Ivan Chee Hong LAI Minoru FUJISHIMA
	Summary \| Full Text:PDF (955.2KB)

pp.829-835 PAPER-Analog and Communications Daisy Chain Transmitter for Power Reduction in Inductive-Coupling CMOS Link Kiichi NIITSU Noriyuki MIURA Mari INOUE Yoshihiro NAKAGAWA Masamoto TAGO Masayuki MIZUNO Takayasu SAKURAI Tadahiro KURODA
	Summary \| Full Text:PDF (1.7MB)

pp.836-841 PAPER-INVITED Device Design of Nanoscale MOSFETs Considering the Suppression of Short Channel Effects and Characteristics Variations Toshiro HIRAMOTO Toshiharu NAGUMO Tetsu OHTOU Kouki YOKOYAMA
	Summary \| Full Text:PDF (1.3MB)

pp.842-847 PAPER-Device Source/Drain Optimization of Double Gate FinFET Considering GIDL for Low Standby Power Devices Katsuhiko TANAKA Kiyoshi TAKEUCHI Masami HANE
	Summary \| Full Text:PDF (617.5KB)

pp.848-855 PAPER-Device Chip-Level Performance Maximization Using ASIS (Application-Specific Interconnect Structure) Wiring Design Concept for 45 nm CMOS Generation Noriaki ODA Hironori IMURA Naoyoshi KAWAHARA Masayoshi TAGAMI Hiroyuki KUNISHIMA Shuji SONE Sadayuki OHNISHI Kenta YAMADA Yumi KAKUHARA Makoto SEKINE Yoshihiro HAYASHI Kazuyoshi UENO
	Summary \| Full Text:PDF (2.3MB)

Regular Section

pp.856-864 PAPER-Optoelectronics All Optical Analog-to-Digital Conversion by Polarization Modulation Using Nonlinear Phase Shift Yoshitomo SHIRAMIZU Nobuo GOTO
	Summary \| Full Text:PDF (627.2KB)

pp.865-876 PAPER-Electronic Circuits Adaptive Supply Voltage for Low-Power Ripple-Carry and Carry-Select Adders Hiroaki SUZUKI Woopyo JEONG Kaushik ROY
	Summary \| Full Text:PDF (1.5MB)

pp.877-884 PAPER-Electronic Circuits A Current-Steering DAC Architecture with Novel Switching Scheme for GPON Burst-Mode Laser Drivers Wei CHEN Johan BAUWELINCK Peter OSSIEUR Xing-Zhi QIU Jan VANDEWEGE
	Summary \| Full Text:PDF (858.9KB)

pp.885-894 PAPER-Semiconductor Materials and Devices Shot Noise Modeling in Metal-Oxide-Semiconductor Field Effect Transistors under Sub-Threshold Condition Yoshioki ISOBE Kiyohito HARA Dondee NAVARRO Youichi TAKEDA Tatsuya EZAKI Mitiko MIURA-MATTAUSCH
	Summary \| Full Text:PDF (713.2KB)

pp.895-902 PAPER-Integrated Electronics A CMOS Temperature Sensor Circuit Takashi OHZONE Tatsuaki SADAMOTO Takayuki MORISHITA Kiyotaka KOMOKU Toshihiro MATSUDA Hideyuki IWATA
	Summary \| Full Text:PDF (870.5KB)

pp.903-906 LETTER-Electromagnetic Theory Low Grazing Scattering from Periodic Neumann Surface with Finite Extent Junichi NAKAYAMA Kazuhiro HATTORI Yasuhiko TAMURA
	Summary \| Full Text:PDF (195.1KB)

pp.907-910 LETTER-Microwaves, Millimeter-Waves A Cost-Effective Transition between a Microstrip Line and a Post-Wall Waveguide Using a Laminated LTCC Substrate in 60-GHz Band Takafumi KAI Jiro HIROKAWA Makoto ANDO Hiroshi NAKANO Yasutake HIRACHI
	Summary \| Full Text:PDF (914.7KB)