IEICE TRANSACTIONS on Electronics

Archive Index

Online ISSN : 1745-1353
Volume E89-C No.3  (Publication Date:2006/03/01)
Previous | 
Next
RSS Feed(Latest Issue) >>  Learn more
Special Section on VLSI Design Technology in the Sub-100 nm Era

pp.211-212  FOREWORD
FOREWORD
Akira MATSUZAWA 
Summary |  Full Text:PDF (41.6KB)

pp.213-220  PAPER-INVITED
System LSI: Challenges and Opportunities
Tadahiro KURODA 
Summary |  Full Text:PDF (3.2MB)

pp.221-229  PAPER-INVITED
Design Philosophy of a Networking-Oriented Data-Driven Processor: CUE
Hiroaki NISHIKAWA 
Summary |  Full Text:PDF (1023.4KB)

pp.230-242  PAPER-System LSIs and Microprocessors
VLSI Architecture Study of a Real-Time Scalable Optical Flow Processor for Video Segmentation
Noriyuki MINEGISHI  Junichi MIYAKOSHI  Yuki KURODA  Tadayoshi KATAGIRI  Yuki FUKUYAMA  Ryo YAMAMOTO  Masayuki MIYAMA  Kousuke IMAMURA  Hideo HASHIMOTO  Masahiko YOSHIMOTO 
Summary |  Full Text:PDF (4.2MB)

pp.243-249  PAPER-System LSIs and Microprocessors
A Fast Elliptic Curve Cryptosystem LSI Embedding Word-Based Montgomery Multiplier
Jumpei UCHIDA  Nozomu TOGAWA  Masao YANAGISAWA  Tatsuo OHTSUKI 
Summary |  Full Text:PDF (260.4KB)

pp.250-262  PAPER-INVITED
Low-Voltage and Low-Power Logic, Memory, and Analog Circuit Techniques for SoCs Using 90 nm Technology and Beyond
Koichiro ISHIBASHI  Tetsuya FUJIMOTO  Takahiro YAMASHITA  Hiroyuki OKADA  Yukio ARIMA  Yasuyuki HASHIMOTO  Kohji SAKATA  Isao MINEMATSU  Yasuo ITOH  Haruki TODA  Motoi ICHIHASHI  Yoshihide KOMATSU  Masato HAGIWARA  Toshiro TSUKADA 
Summary |  Full Text:PDF (2.1MB)

pp.263-270  PAPER-INVITED
Module-Wise Dynamic Voltage and Frequency Scaling for a 90 nm H.264/MPEG-4 Codec LSI
Yukihito OOWAKI  Shinichiro SHIRATAKE  Toshihide FUJIYOSHI  Mototsugu HAMADA  Fumitoshi HATORI  Masami MURAKATA  Masafumi TAKAHASHI 
Summary |  Full Text:PDF (944.1KB)

pp.271-279  PAPER-Low Power Techniques
Low Dynamic Power and Low Leakage Power Techniques for CMOS Motion Estimation Circuits
Nobuaki KOBAYASHI  Tomomi EI  Tadayoshi ENOMOTO 
Summary |  Full Text:PDF (1.2MB)

pp.280-286  PAPER-Low Power Techniques
Low-Power Low-Leakage FPGA Design Using Zigzag Power Gating, Dual-VTH/VDD and Micro-VDD-Hopping
Canh Quang TRAN  Hiroshi KAWAGUCHI  Takayasu SAKURAI 
Summary |  Full Text:PDF (953.5KB)

pp.287-294  PAPER-Low Power Techniques
Reducing Consuming Clock Power Optimization of a 90 nm Embedded Processor Core
Tetsuya YAMADA  Masahide ABE  Yusuke NITTA  Kenji OGURA  Manabu KUSAOKE  Makoto ISHIKAWA  Motokazu OZAWA  Kiwamu TAKADA  Fumio ARAKAWA  Osamu NISHII  Toshihiro HATTORI 
Summary |  Full Text:PDF (1.4MB)

pp.295-299  PAPER-Low Power Techniques
A 1 V Phase Locked Loop with Leakage Compensation in 0.13 µm CMOS Technology
Chi-Nan CHUANG  Shen-Iuan LIU 
Summary |  Full Text:PDF (1.7MB)

pp.300-313  PAPER-INVITED
Circuits for CMOS High-Speed I/O in Sub-100 nm Technologies
Hirotaka TAMURA  Masaya KIBUNE  Hisakatsu YAMAGUCHI  Kouichi KANDA  Kohtaroh GOTOH  Hideki ISHIDA  Junji OGAWA 
Summary |  Full Text:PDF (1MB)

pp.314-319  PAPER-Interface and Interconnect Techniques
Channel-Count-Independent BIST for Multi-Channel SerDes
Kouichi YAMAGUCHI  Muneo FUKAISHI 
Summary |  Full Text:PDF (658.8KB)

pp.320-326  PAPER-Interface and Interconnect Techniques
A 1.2 Gbps Non-contact 3D-Stacked Inter-Chip Data Communications Technology
Daisuke MIZOGUCHI  Noriyuki MIURA  Takayasu SAKURAI  Tadahiro KURODA 
Summary |  Full Text:PDF (905.4KB)

pp.327-333  PAPER-Interface and Interconnect Techniques
Alternate Self-Shielding for High-Speed and Reliable On-Chip Global Interconnect
Yoichi YUYAMA  Akira TSUCHIYA  Kazutoshi KOBAYASHI  Hidetoshi ONODERA 
Summary |  Full Text:PDF (877.7KB)

pp.334-341  PAPER-Interface and Interconnect Techniques
An Automatic Bi-Directional Bus Repeater Control Scheme Using Dynamic Collaborative Driving Techniques
Masahiro NOMURA  Taku OHSAWA  Koichi TAKEDA  Yoetsu NAKAZAWA  Yoshinori HIROTA  Yasuhiko HAGIHARA  Naoki NISHI 
Summary |  Full Text:PDF (799.4KB)

pp.342-348  PAPER-INVITED
Variability: Modeling and Its Impact on Design
Hidetoshi ONODERA 
Summary |  Full Text:PDF (530.3KB)

pp.349-355  PAPER-Signal Integrity and Variability
A Statistical Quality Model for Delay Testing
Yasuo SATO  Shuji HAMADA  Toshiyuki MAEDA  Atsuo TAKATORI  Seiji KAJIHARA 
Summary |  Full Text:PDF (935.3KB)

pp.356-363  PAPER-Signal Integrity and Variability
Multi-Ported Register File for Reducing the Impact of PVT Variation
Yuuichirou IKEDA  Masaya SUMITA  Makoto NAGATA 
Summary |  Full Text:PDF (1.3MB)

pp.364-369  PAPER-Signal Integrity and Variability
Feedforward Active Substrate Noise Cancelling Based on di/dt of Power Supply
Toru NAKURA  Makoto IKEDA  Kunihiro ASADA 
Summary |  Full Text:PDF (674.6KB)

pp.370-376  PAPER-Signal Integrity and Variability
On-Chip Detector for Single-Event Noise Sensing with Voltage Scaling Function
Mohamed ABBAS  Makoto IKEDA  Kunihiro ASADA 
Summary |  Full Text:PDF (591.5KB)

pp.377-383  PAPER-CAD
Cell Library Development Methodology for Throughput Enhancement of Character Projection Equipment
Makoto SUGIHARA  Taiga TAKATA  Kenta NAKAMURA  Ryoichi INANAMI  Hiroaki HAYASHI  Katsumi KISHIMOTO  Tetsuya HASEBE  Yukihiro KAWANO  Yusuke MATSUNAGA  Kazuaki MURAKAMI  Katsuya OKUMURA 
Summary |  Full Text:PDF (429.1KB)

pp.384-391  PAPER-Soft Error
Soft Error Hardened Latch Scheme with Forward Body Bias in a 90-nm Technology and Beyond
Yoshihide KOMATSU  Yukio ARIMA  Koichiro ISHIBASHI 
Summary |  Full Text:PDF (1.3MB)

pp.392-394  LETTER-Interconnect Technique
Trends of On-Chip Interconnects in Deep Sub-Micron VLSI
Danardono Dwi ANTONO  Kenichi INAGAKI  Hiroshi KAWAGUCHI  Takayasu SAKURAI 
Summary |  Full Text:PDF (1.1MB)

Regular Section

pp.395-402  PAPER-Electromagnetic Theory
Propagation Analysis of Circular Surface Waveguides with a Periodically Corrugated Ground Plane
Chin-Jui LAI  Ching-Her LEE  Chung-I G. HSU  Jean-Fu KIANG 
Summary |  Full Text:PDF (424.9KB)

pp.403-409  PAPER-Microwaves, Millimeter-Waves
Aperture-Backed Microstrip-Line Stepped-Impedance Resonators and Transformers for Performance-Enhanced Bandpass Filters
Hang WANG  Lei ZHU 
Summary |  Full Text:PDF (873.3KB)

pp.410-419  PAPER-Electronic Components
Extraction of LRGC Matrices for 8-Coupled Uniform Lossy Transmission Lines Using 2-Port VNA Measurements
Hyun Bae LEE  Kyoungho LEE  Hae Kang JUNG  Hong June PARK 
Summary |  Full Text:PDF (2.2MB)

pp.420-428  PAPER-Integrated Electronics
A Fast Switching Low Phase Noise CMOS Frequency Synthesizer with a New Coarse Tuning Method for PHS Applications
Kang-Yoon LEE  Hyunchul KU  Young Beom KIM 
Summary |  Full Text:PDF (1.7MB)

pp.429-433  PAPER-Electronic Displays
Evaluation of the Fusional Limit between the Front and Rear Images in Depth-Fused 3-D Visual Illusion
Hideaki TAKADA  Shiro SUYAMA  Munekazu DATE 
Summary |  Full Text:PDF (498.9KB)

pp.434-436  LETTER-Electromagnetic Theory
A New Approach to Mixed-Path Propagation of Surface Wave
Bin-hao JIANG 
Summary |  Full Text:PDF (86.9KB)

pp.437-439  LETTER-Lasers, Quantum Electronics
Quantum Noise and Feed-Back Noise in Blue-Violet InGaN Semiconductor Lasers
Kenjiro MATSUOKA  Kazushi SAEKI  Eiji TERAOKA  Minoru YAMADA  Yuji KUWAMURA 
Summary |  Full Text:PDF (250.4KB)

pp.440-442  LETTER-Electronic Circuits
Low Power Low Phase Noise LC Quadrature VCO Topology
Ji-Hoon KIM  Hyung-Joun YOO 
Summary |  Full Text:PDF (222.6KB)

Previous | 
Next
go to Page Top