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Online ISSN : 1745-1353

Volume E89-C No.11 (Publication Date:2006/11/01)

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Special Section on Novel Device Architectures and System Integration Technologies

pp.1491-1491 FOREWORD FOREWORD Takahiro HANYU
	Summary \| Full Text:PDF (50.6KB)

pp.1492-1498 PAPER-INVITED Solid-Electrolyte Nanometer Switch Naoki BANNO Toshitsugu SAKAMOTO Noriyuki IGUCHI Hisao KAWAURA Shunichi KAERIYAMA Masayuki MIZUNO Kozuya TERABE Tsuyoshi HASEGAWA Masakazu AONO
	Summary \| Full Text:PDF (1MB)

pp.1499-1503 PAPER-INVITED Carbon Nanotube Technologies for LSI via Interconnects Yuji AWANO
	Summary \| Full Text:PDF (2.9MB)

pp.1504-1511 PAPER-INVITED Single-Electron Logic Systems Based on a Graphical Representation of Digital Functions Yoshihito AMEMIYA
	Summary \| Full Text:PDF (1.1MB)

pp.1512-1518 PAPER-INVITED Design and Evaluation of a Massively Parallel Processor Based on Matrix Architecture Toru SHIMIZU Masami NAKAJIMA Masahiro KAINAGA
	Summary \| Full Text:PDF (1.8MB)

pp.1519-1525 PAPER An On-Chip Supply-Voltage Control System Considering PVT Variations for Worst-Caseless Lower Voltage SoC Design Takayuki GYOHTEN Fukashi MORISHITA Isamu HAYASHI Mako OKAMOTO Hideyuki NODA Katsumi DOSAKA Kazutami ARIMOTO Yasutaka HORIBA
	Summary \| Full Text:PDF (1.5MB)

pp.1526-1534 PAPER A Differential Cell Terminal Biasing Scheme Enabling a Stable Write Operation against a Large Random Threshold Voltage (V_th) Variation Hiroyuki YAMAUCHI Toshikazu SUZUKI Yoshinobu YAMAGAMI
	Summary \| Full Text:PDF (7.4MB)

pp.1535-1543 PAPER An Integrated Timing and Dynamic Supply Noise Verification for Multi-10-Million Gate SoC Designs Kenji SHIMAZAKI Makoto NAGATA Mitsuya FUKAZAWA Shingo MIYAHARA Masaaki HIRATA Kazuhiro SATOH Hiroyuki TSUJIKAWA
	Summary \| Full Text:PDF (1.6MB)

pp.1544-1550 PAPER Chip-Level Performance Improvement Using Triple Damascene Wiring Design Concept for the 0.13 µm CMOS Generation and Beyond Noriaki ODA Hiroyuki KUNISHIMA Takashi KYOUNO Kazuhiro TAKEDA Tomoaki TANAKA Toshiyuki TAKEWAKI Masahiro IKEDA
	Summary \| Full Text:PDF (1.4MB)

pp.1551-1558 PAPER Minimizing Energy Consumption Based on Dual-Supply-Voltage Assignment and Interconnection Simplification Masanori HARIYAMA Shigeo YAMADERA Michitaka KAMEYAMA
	Summary \| Full Text:PDF (1.2MB)

pp.1559-1566 PAPER Measurement-Based Analysis of Delay Variation Induced by Dynamic Power Supply Noise Mitsuya FUKAZAWA Makoto NAGATA
	Summary \| Full Text:PDF (938KB)

pp.1567-1574 PAPER High-Frequency Low-Noise Voltage-Controlled LC-Tank Oscillators Using a Tunable Inductor Technique Ching-Yuan YANG Meng-Ting TSAI
	Summary \| Full Text:PDF (1.2MB)

pp.1575-1580 PAPER Design and Evaluation of a NULL-Convention Circuit Based on Dual-Rail Current-Mode Differential Logic Naoya ONIZAWA Takahiro HANYU
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pp.1581-1590 PAPER Back-End Design of a Collision-Resistive RFID System through High-Level Modeling Approach Yohei FUKUMIZU Makoto NAGATA Kazuo TAKI
	Summary \| Full Text:PDF (1.5MB)

pp.1591-1597 PAPER Design of a Low-Power Quaternary Flip-Flop Based on Dynamic Differential Logic Akira MOCHIZUKI Hirokatsu SHIRAHAMA Takahiro HANYU
	Summary \| Full Text:PDF (1.2MB)

pp.1598-1604 PAPER Implementation of a High-Speed Asynchronous Data-Transfer Chip Based on Multiple-Valued Current-Signal Multiplexing Tomohiro TAKAHASHI Takahiro HANYU
	Summary \| Full Text:PDF (17.1MB)

pp.1605-1611 PAPER Vision Chip Architecture for Detecting Line of Sight Including Saccade Junichi AKITA Hiroaki TAKAGI Takeshi NAGASAKI Masashi TODA Toshio KAWASHIMA Akio KITAGAWA
	Summary \| Full Text:PDF (3.1MB)

pp.1612-1619 PAPER A Reliability-Enhanced TCAM Architecture with Associated Embedded DRAM and ECC Hideyuki NODA Katsumi DOSAKA Hans Jurgen MATTAUSCH Tetsushi KOIDE Fukashi MORISHITA Kazutami ARIMOTO
	Summary \| Full Text:PDF (1.2MB)

pp.1620-1628 PAPER Cache-Based Network Processor Architecture: Evaluation with Real Network Traffic Michitaka OKUNO Shinji NISHIMURA Shin-ichi ISHIDA Hiroaki NISHI
	Summary \| Full Text:PDF (1.7MB)

pp.1629-1636 PAPER A Power- and Area-Efficient SRAM Core Architecture with Segmentation-Free and Horizontal/Vertical Accessibility for Super-Parallel Video Processing Junichi MIYAKOSHI Yuichiro MURACHI Tomokazu ISHIHARA Hiroshi KAWAGUCHI Masahiko YOSHIMOTO
	Summary \| Full Text:PDF (1.7MB)

pp.1637-1644 PAPER A VLSI Spiking Feedback Neural Network with Negative Thresholding and Its Application to Associative Memory Kan'ya SASAKI Takashi MORIE Atsushi IWATA
	Summary \| Full Text:PDF (994KB)

pp.1645-1654 PAPER Systematic Interpretation of Redundant Arithmetic Adders in Binary and Multiple-Valued Logic Naofumi HOMMA Takafumi AOKI Tatsuo HIGUCHI
	Summary \| Full Text:PDF (856.7KB)

pp.1655-1661 PAPER A Multi-Context FPGA Using Floating-Gate-MOS Functional Pass-Gates Masanori HARIYAMA Sho OGATA Michitaka KAMEYAMA
	Summary \| Full Text:PDF (867.1KB)

pp.1662-1669 PAPER CMOS Image Sensor Using Negative-Feedback Resetting to Obtain Variably Smoothed Images Masayuki IKEBE Keita SAITO
	Summary \| Full Text:PDF (1.2MB)

pp.1670-1673 LETTER A Low-Power Write Driver for Hard Disk Drives Tatsuya KAWASHIMO Hiroki YAMASHITA Masayoshi YAGYU Fumio YUKI
	Summary \| Full Text:PDF (1.1MB)

pp.1674-1675 LETTER A Cost Effective Interconnection Network for Reconfigurable Computing Processor in Digital Signal Processing Applications Yeong-Kang LAI Lien-Fei CHEN Jian-Chou CHEN Chun-Wei CHIU
	Summary \| Full Text:PDF (6MB)

Regular Section

pp.1676-1681 PAPER-Electromagnetic Theory Error Analysis of the Multilevel Fast Multipole Algorithm Shinichiro OHNUKI Weng Cho CHEW
	Summary \| Full Text:PDF (1.1MB)

pp.1682-1688 PAPER-Electronic Circuits Spread-Spectrum Clock Generator for Serial ATA with Multi-Bit ΣΔ Modulator-Controlled Fractional PLL Masaru KOKUBO Takashi KAWAMOTO Takashi OSHIMA Takayuki NOTO Masato SUZUKI Shigeyuki SUZUKI Takashi HAYASAKA Tomoaki TAKAHASHI Jun KASAI
	Summary \| Full Text:PDF (769.8KB)

pp.1689-1694 PAPER-Electronic Circuits Autonomous di/dt Control of Power Supply for Margin Aware Operation Toru NAKURA Makoto IKEDA Kunihiro ASADA
	Summary \| Full Text:PDF (841.3KB)

pp.1695-1699 PAPER-Electronic Instrumentation and Control Calculation of Measurement Uncertainties of Synchronously Sampled AC Signals in Nonideal Synchronization with Fundamental Frequency Predrag PETROVIC
	Summary \| Full Text:PDF (225.4KB)

pp.1700-1703 LETTER-Electromagnetic Theory Wave Absorber Formed by Arranging Cylindrical Bars at Intervals for Installing between ETC Lanes Kouta MATSUMOTO Takeru OZAWA Takuya NAKAMURA Takahiro AOYAGI Osamu HASHIMOTO Takashi MIYAMOTO
	Summary \| Full Text:PDF (369.5KB)

pp.1704-1707 LETTER-Microwaves, Millimeter-Waves High Efficiency Open Collector Adaptive Bias SiGe HBT Differential Power Amplifier Kuei-Cheng LIN Tsung-Yu YANG Kuan-Yu CHEN Hwann-Kaeo CHIOU
	Summary \| Full Text:PDF (655.7KB)

pp.1708-1712 LETTER-Microwaves, Millimeter-Waves Mode Converter Optimization for U-Style Rotary Joint Dong-Hyun KIM Jeong-Woo JWA Doo-Yeong YANG
	Summary \| Full Text:PDF (258.5KB)

pp.1713-1718 LETTER-Microwaves, Millimeter-Waves Passive Reduced-Order Macro-Modeling for Linear Time-Delay Interconnect Systems Wenliang TSENG Chien-Nan Jimmy LIU Chauchin SU
	Summary \| Full Text:PDF (205.7KB)