IEICE TRANSACTIONS on Electronics

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Volume E80-C No.7  (Publication Date:1997/07/25)
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Special Issue on New Concept Device and Novel Architecture LSIs

pp.839-840  FOREWORD
FOREWORD
Fujio MASUOKA  
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pp.841-848  INVITED PAPER
Functionality Enhancement in Elemental Devices for Implementing Intelligence on Integrated Circuits
Tadahiro OHMI  Tadashi SHIBATA  
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pp.849-858  INVITED PAPER
Eliciting the Potential Functions of Single-Electron Circuits
Masamichi AKAZAWA  Yoshihito AMEMIYA  
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pp.859-867  INVITED PAPER
A 3.2 GFLOPS Neural Network Accelerator
Shinji KOMORI  Yutaka ARIMA  Yoshikazu KONDO  Hirono TSUBOTA  Ken-ichi TANAKA  Kazuo KYUMA  
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pp.868-874  INVITED PAPER
CAM-Based Highly-Parallel Image Processing Hardware
Takeshi OGURA  Mamoru NAKANISHI  
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pp.875-880  PAPER-Quantum Devices
Surface Tunnel Transistors with Multiple Interband Tunnel Junctions
Toshio BABA  Tetsuya UEMURA  
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pp.881-885  PAPER-Quantum Devices
Proposal of a Schottky-Barrier SET Aiming at a Future Integrated Device
Minoru FUJISHIMA  Hironobu FUKUI  Shuhei AMAKAWA  Koichiro HOH  
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pp.886-892  PAPER-Novel Structure Devices
SOI/CMOS Circuit Design for High-Speed Communication LSIs
Kimio UEDA  Yoshiki WADA  Takanori HIROTA  Shigenobu MAEDA  Koichiro MASHIKO  Hisanori HAMANO  
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pp.893-898  PAPER-Novel Structure Devices
Simulated Device Design Optimization to Reduce the Floating Body Effect for Sub-Quarter Micron Fully Depleted SOI-MOSFETs
Risho KOH  Tohru MOGAMI  Haruo KATO  
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pp.899-904  PAPER-Novel Structure Devices
A Long Data Retention SOI DRAM with the Body Refresh Function
Shigeki TOMISHIMA  Fukashi MORISHITA  Masaki TSUKUDE  Tadato YAMAGATA  Kazutami ARIMOTO  
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pp.905-910  PAPER-Novel Structure Devices
An Accurate Model of Fully-Depleted Surrounding Gate Transistor (FD-SGT)
Tetsuo ENDOH  Tairiku NAKAMURA  Fujio MASUOKA  
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pp.911-917  PAPER-Novel Structure Devices
An Analytic Steady-State Current-Voltage Characteristics of Short Channel Fully-Depleted Surrounding Gate Transistor (FD-SGT)
Tetsuo ENDOH  Tairiku NAKAMURA  Fujio MASUOKA  
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pp.918-923  PAPER-Novel Concept Devices
Novel Electronic Properties on Ferroelectric/ferromagnetic Heterostructures
Hitoshi TABATA  Tomoji KAWAI  
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pp.924-930  PAPER-Novel Concept Devices
Low Power Neuron-MOS Technology for High-Functionality Logic Gate Synthesis
Ho-Yup KWON  Koji KOTANI  Tadashi SHIBATA  Tadahiro OHMI  
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pp.931-934  PAPER-Novel Concept Devices
Design of an Excitable Field Towards a Novel Parallel Computation
Kenichi YOSHIKAWA  Ikuko MOTOIKE  Kimiko KAJIYA  
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pp.935-940  PAPER-Novel Concept Devices
Design and Analysis of Multiwave Interconnection Networks for MCM-Based Parallel Processing
Takafumi AOKI  Shinichi SHIONOYA  Tatsuo HIGUCHI  
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pp.941-947  PAPER-Multiple-Valued Architectures
Design and Implementation of a Low-Power Multiple-Valued Current-Mode Integrated Circuit with Current-Source Control
Takahiro HANYU  Satoshi KAZAMA  Michitaka KAMEYAMA  
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pp.948-955  PAPER-Multiple-Valued Architectures
Design and Evaluation of a 4-Valued Universal-Literal CAM for Cellular Logic Image Processing
Takahiro HANYU  Manabu ARAKAKI  Michitaka KAMEYAMA  
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pp.956-961  PAPER-Multi Processors
An Image Scanning Method with Selective Activation of Tree Structure
Junichi AKITA  Kunihiro ASADA  
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pp.962-969  PAPER-Multi Processors
Hardware Framework for Accelerating the Execution Speed of a Genetic Algorithm
Barry SHACKLEFORD  Etsuko OKUSHI  Mitsuhiro YASUDA  Hisao KOIZUMI  Katsuhiko SEO  Takashi IWAMOTO  
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pp.970-975  PAPER-Multi Processors
A Memory-Based Parallel Processor for Vector Quantization: FMPP-VQ
Kazutoshi KOBAYASHI  Masayoshi KINOSHITA  Hidetoshi ONODERA  Keikichi TAMARU  
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pp.976-982  PAPER-Neural Networks and Chips
A Digital Neuro Chip with Proliferating Neuron Architecture
Hiroyuki NAKAHIRA  Masaru FUKUDA  Akira YAMAMOTO  Shiro SAKIYAMA  Masakatsu MARUYAMA  
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pp.983-989  PAPER-Neural Networks and Chips
A Learning Algorithm for a Neural Network LSI with Restricted Integer Weights
Tomohisa KIMURA  Takeshi SHIMA  
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pp.990-995  PAPER-Neural Networks and Chips
Self-Learning Analog Neural Network LSI with High-Resolution Non-Volatile Analog Memory and a Partially-Serial Weight-Update Architecture
Takashi MORIE  Osamu FUJITA  Kuniharu UCHIMURA  
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pp.996-1002  PAPER-Neural Networks and Chips
A Sparse Memory Access Architecture for Digital Neural Network LSIs
Kimihisa AIHARA  Osamu FUJITA  Kuniharu UCHIMURA  
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pp.1003-1009  PAPER-Neural Networks and Chips
A Wavelet View for Unifying Boolean Discrete Functions and Neural Nets through Haar Transform
Masatoshi SEKINE  
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pp.1010-1015  PAPER-Neural Networks and Chips
A Novel Narrow-Band Bandpass Filter and Its Application to SSB Communication
Xiaoxing ZHANG  Masahiro IWAHASHI  Noriyoshi KAMBAYASHI  
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pp.1016-1024  PAPER-Integrated Electronics
Power Optimization for Data Compressors Based on a Window Detector in a 5454 Bit Multiplier
Minkyu SONG  Kunihiro ASADA  
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pp.1025-1042  PAPER-Electronic Circuits
Model for Thermal Noise in Semiconductor Bipolar Transistors at Low-Current Operation as Multidimensional Diffusion Stochastic Process
Yevgeny V.MAMONTOV  Magnus WILLANDER  
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pp.1043-1055  PAPER-Recording and Memory Technologies
Influence of the Relaxation Current in BaxSr(1-x) TiO3 Thin Film Capacitors on DRAM Operation
Ken NUMATA  Yukio FUKUDA  Katsuhiro AOKI  Yasutoshi OKUNO  Akitoshi NISHIMURA  
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pp.1056-1062  PAPER-Electromagnetic Theory
Uniform Physical Optics Diffraction Coefficients for Impedance Surfaces and Apertures
Masayuki OODO  Makoto ANDO  
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pp.1063-1066  LETTER-Electronic Circuits
A Current-Mode Analog Chaos Circuit Realizing a Henon Map
Kei EGUCHI  Takahiro INOUE  
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pp.1067-1069  LETTER-Opto-Electronics
Model for Estimating Bending Loss in the 1.5 µm Wavelength Region
Kyozo TSUJIKAWA  Masaharu OHASHI  Osamu KAWATA  
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