IEICE TRANSACTIONS on Electronics

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Volume E80-C No.12  (Publication Date:1997/12/25)
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Special Issue on Low-Power and High-Speed LSI Technologies

pp.1509-1510  FOREWORD
FOREWORD
Masachika HARADA  
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pp.1511-1522  INVITED PAPER
Low-Power Circuit Design Techniques for Si Bipolar Gbit/s LSIsAn Overview
Haruhiko ICHINO  
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pp.1523-1531  INVITED PAPER
Low-Power and High-Speed Advantages of DRAM-Logic Integration for Multimedia Systems
Takao WATANABE  Ryo FUJITA  Kazumasa YANAGISAWA  
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pp.1532-1538  INVITED PAPER
Low-Power and High-Speed LSIs Using 0.25-µm CMOS/SIMOX
Masayuki INO  
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pp.1539-1545  INVITED PAPER
Design and Architecture for Low-Power/High-Speed RISC Microprocessor: SuperH
Hideo MAEJIMA  Masahiro KAINAGA  Kunio UCHIYAMA  
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pp.1546-1552  PAPER
A 100 MIPS High Speed and Low Power Digital Signal Processor
Hiroshi TAKAHASHI  Shigeshi ABIKO  Shintaro MIZUSHIMA  Yuji OZAWA  Kenichi TASHIRO  Shigetoshi MURAMATSU  Masahiro FUSUMADA  Akemi TODOROKI  Youichi TANAKA  Masayasu ITOIGAWA  Isao MORIOKA  Hiroyuki MIZUNO  Miki KOJIMA  Giovanni NASO  Emmanuel EGO  Frank CHIRAT  
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pp.1553-1559  PAPER
A 10-bit 50 MS/s 300 mW A/D Converter Using Reference Feed-Forward Architecture
Takashi OKUDA  Osamu MATSUMOTO  Toshio KUMAMOTO  Masao ITO  Hiroyuki MOMONO  Takahiro MIKI  Takeshi TOKUDA  
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pp.1560-1571  PAPER
A 0.18-µm CMOS Hot-Standby PLL Using a Noise-Immune Adaptive-Gain VCO
Masayuki MIZUNO  Koichiro FURUTA  Takeshi ANDOH  Akira TANABE  Takao TAMURA  Hidenobu MIYAMOTO  Akio FURUKAWA  Masakazu YAMASHINA  
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pp.1572-1577  PAPER
A Low Power Data Storage Circuit with an Intermittent Power Supply Scheme for Sub-1 V MT-CMOS LSIs
Hironori AKAMATSU  Toru IWATA  Hiroyuki YAMAUCHI  Hisakazu KOTANI  Akira MATSUZAWA  Hiro YAMAMOTO  Takashi HIRATA  
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pp.1578-1585  PAPER
A CAD-Based Low-Power Design Methodology for Very High-Speed Si Bipolar Standard Cell LSIs
Keiichi KOIKE  Kenji KAWAI  Akira ONOZAWA  Yuichiro TAKEI  Yoshiji KOBAYASHI  Haruhiko ICHINO  
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pp.1586-1591  PAPER
A Buried-Channel Self-Aligned GaAs MESFET with High Power-Efficiency and Low Noise-Figure for 1.9-GHz Single-Chip Front-End MMICs
Kazuya NISHIHORI  Atsushi KAMEYAMA  Yoshiaki KITAURA  Yoshikazu TANABE  Masakatsu MIHARA  Misao YOSHIMURA  Mayumi HIROSE  Naotaka UCHITOMI  
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pp.1592-1597  PAPER
Low-Voltage Operation GaAs Receiver Front-End IC
Junji ITOH  Tadayoshi NAKATSUKA  Mitsuru NISHITSUJI  Tomoya UDA  Osamu ISHIKAWA  
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pp.1598-1607  PAPER-Integrated Electronics
A Switched Virtual-GND Level Technique for Fast and Low Power SRAM's
Nobutaro SHIBATA  
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pp.1608-1613  PAPER-Microwave and Millimeter Wave Technology
Analysis of Coupling between CPW-Fed Slot Antennas Using FDTD with PML Boundary Conditions
Seppo SAARIO  Yongxi QIAN  Eikichi YAMASHITA  
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pp.1614-1621  PAPER-Microwave and Millimeter Wave Technology
Dual-Frequency Matching Technique and Its Application to an Octave-Band (30-60 GHz) MMIC Amplifier
Hiroki NAKAJIMA  Masahiro MURAGUCHI  
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pp.1622-1623  LETTER-Electronic Circuits
Theoretical Analysis of a Switched-Capacitor Wien Bridge Oscillator
Yuuji HORIE  Masahiro TERAMURA  Chikara MINAMITAKE  Tomoyuki MIYAZAKI  
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pp.1624-1627  LETTER-Electronic Circuits
A 40-Gbit/s Decision IC Fabricated with 0.12-µm GaAs MESFETs
Koichi MURATA  Taiichi OTSUJI  Mikio YONEYAMA  Masami TOKUMITSU  
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