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Volume E79-C No.7  (Publication Date:1996/07/25)
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Special Issue on the 1995 Symposium on VLSI Circuits (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.31, No.4 April 1996)

pp.881-882  FOREWORD
FOREWORD
Atsushi IWATA  Ian YOUNG  
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pp.883-891  PAPER-Communications
A 2.5-Gb/s 15-mW Clock Recovery Circuit
Behzad RAZAVI  
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pp.892-897  PAPER-Communications
46 Gb/s DEMUX, 50 Gb/s MUX, and 30 GHz Static Frequency Divider in Silicon Bipolar Technology
Alfred FELDER  Michael MOLLER  Josef POPP  Josef BOCK  Hans-Martin REIN  
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pp.898-904  PAPER-Logic
A 250-622 MHz Deskew and Jitter-Suppressed Clock Buffer Using Two-Loop Architecture
Satoru TANOI  Tetsuya TANABE  Kazuhiko TAKAHASHI  Sanpei MIYAMOTO  Masaru UESUGI  
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pp.905-914  PAPER-Logic
An 80-MOPS-Peak High-Speed and Low-Power-Consumption 16-b Digital Signal Processor
Hideyuki KABUO  Minoru OKAMOTO  Isao TANAKA  Hiroyuki YASOSHIMA  Shinichi MARUI  Masayuki YAMASAKI  Toshio SUGIMURA  Katsuhiko UEDA  Toshihiro ISHIKAWA  Hidetoshi SUZUKI  Ryuichi ASAHI  
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pp.915-924  PAPER-Logic
A 286 MHz 64-b Floating Point Multiplier with Enhanced CG Operation
Hiroshi MAKINO  Hiroaki SUZUKI  Hiroyuki MORINAKA  Yasunobu NAKASE  Koichiro MASHIKO  Tadashi SUMI  
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pp.925-933  PAPER-Logic
An Efficient Charge Recovery Logic Circuit
Yong MOON  Deog-kyoon JEONG  
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pp.934-941  PAPER-Interface Circuits
A Low Power and High Speed Data Transfer Scheme with Asynchronous Compressed Pulse Width Modulation for AS-Memory
Tadaaki YAMAUCHI  Yoshikazu MOROOKA  Hideyuki OZAKI  
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pp.942-947  PAPER-Interface Circuits
Capacitance Coupling Immune, Transient Sensitive Accelerator for Resistive Interconnect Signals of Subquarter Micron ULSI
Tomofumi IIMA  Masayuki MIZUNO  Tadahiko HORIUCHI  Masakazu YAMASHINA  
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pp.948-956  PAPER-Memory
A 90-MHz 16-Mb System Integrated Memory with Direct Interface to CPU
Katsumi DOSAKA  Akira YAMAZAKI  Naoya WATANABE  Hideaki ABE  Jun OHTANI  Toshiyuki OGAWA  Kazunori ISHIHARA  Masaki KUMANOYA  
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pp.957-962  PAPER-Memory
A Current Direction Sense Technique for Multiport SRAM's
Masanori IZUMIKAWA  Masakazu YAMASHINA  
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pp.963-968  PAPER-Memory
Driving Source-Line Cell Architecture for Sub-1-V High-Speed Low-Power Applications
Hiroyuki MIZUNO  Takahiro NAGANO  
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pp.969-977  PAPER-Memory
Fault-Tolerant Designs for 256 Mb DRAM
Toshiaki KIRIHATA  Yohji WATANABE  Hing WONG  John K. DEBROSSE  Munehiro YOSHIDA  Daisuke KATO  Shuso FUJII  Matthew R. WORDEMAN  Peter POECHMUELLER  Stephen A. PARKE  Yoshiaki ASAO  
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pp.978-985  PAPER-Memory
A 286 mm2 256 Mb DRAM with 32 Both-Ends DQ
Yohji WATANABE  Hing WONG  Toshiaki KIRIHATA  Dasisuke KATO  John K. DEBROSSE  Takahiko HARA  Munehiro YOSHIDA  Hideo MUKAI  Khandker N. QUADER  Takeshi NAGAI  Peter POECHMUELLER  Peter PFEFFERL  Matthew R. WORDEMAN  Shuso FUJII  
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pp.986-996  PAPER-Memory
A Mixed-Mode Voltage Down Converter with Impedance Adjustment Circuitry for Low-Voltage High-Frequency Memories
Tsukasa OOISHI  Yuichiro KOMIYA  Kei HAMADE  Mikio ASAKURA  Kenichi YASUDA  Kiyohiro FURUTANI  Tetsuo KATO  Hideto HIDAKA  Hideyuki OZAKI  
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pp.997-1002  PAPER-Memory
SOI-DRAM Circuit Technologies for Low Power High Speed Multigiga Scale Memories
Shigehiro KUGE  Fukashi MORISHITA  Takahiro TSURUDA  Shigeki TOMISHIMA  Masaki TSUKUDE  Tadato YAMAGATA  Kazutami ARIMOTO  
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pp.1003-1012  PAPER-Memory
Cell-Plate-Line/Bit-Line Complementary Sensing (CBCS) Architecture for Ultra Low-Power DRAM's
Takeshi HAMAMOTO  Yoshikazu MOROOKA  Mikio ASAKURA  Hideyuki OZAKI  
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pp.1013-1020  PAPER-Memory
A Double-Leve1-Vth Select Gate Array Architecture for Multilevel NAND Flash Memories
Ken TAKEUCHI  Tomoharu TANAKA  Hiroshi NAKAMURA  
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