IEICE TRANSACTIONS on Electronics

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Volume E78-C No.4  (Publication Date:1995/04/25)
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Special Issue on Low-Voltage, Low-Power Integrated Circuits

pp.333-333  FOREWORD
FOREWORD
Katsuhiro SHIMOHIGASHI  
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pp.334-344  INVITED PAPER
Overview of Low-Power ULSI Circuit Techniques
Tadahiro KURODA  Takayasu SAKURAI  
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pp.345-352  INVITED PAPER
Trends in Secondary Batteries for Portable Electronic Equipment
Kazunobu MATSUMOTO  Akira KAWAKAMI  
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pp.353-359  PAPER-Device Technology
High-Speed High-Density Self-Aligned PNP Technology for Low-Power Complementary Bipolar ULSIs
Katsuyoshi WASHIO  Hiromi SHIMAMOTO  Tohru NAKAMURA  
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pp.360-367  PAPER-Device Technology
High-Speed and Low-Power n+-p+ Double-Gate SOI CMOS
Kunihiro SUZUKI  Tetsu TANAKA  Yoshiharu TOSAKA  Hiroshi HORIE  Toshihiro SUGII  
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pp.368-373  PAPER-Device Technology
Monolithic Integration of Resonant Tunneling Diode and HEMT for Low-Voltage, Low-Power Digital Circuits
Yuu WATANABE  Yasuhiro NAKASHA  Kenji IMANISHI  Masahiko TAKIKAWA  
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pp.374-380  PAPER-Digital Circuits
A New Emitter-Follower Circuit for High-Speed and Low-Power ECL
Nagisa SASAKI  Hisayasu SATO  Kimio UEDA  Koichiro MASHIKO  Hiroshi SHIBATA  
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pp.381-388  PAPER-Digital Circuits
A 1.5-V 250-MHz to 3.0-V 622-MHz Operation CMOS Phase-Locked Loop with Precharge Type Phase-Frequency Detector
Harufusa KONDOH  Hiromi NOTANI  Tsutomu YOSHIMURA  Hiroshi SHIBATA  Yoshio MATSUDA  
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pp.389-393  PAPER-Digital Circuits
A 0.9-V, 2.5 MHz CMOS 32-bit Microprocessor
Hiroaki SUZUKI  Toshichika SAKAI  Hisao HARIGAI  Yoichi YANO  
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pp.394-403  PAPER-Digital Circuits
A Low Power Bus Architecture with Local and Global Charge-Recycling Bus Techniques for Battery-Operated Ultra-High Data Rate ULSI's
Hiroyuki YAMAUCHI  Hironori AKAMATSU  Tsutomu FUJITA  
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pp.404-413  PAPER-Digital Circuits
Dynamic Terminations for Low-Power High-Speed Chip Interconnection in Portable Equipment
Takayuki KAWAHARA  Masakazu AOKI  Katsutaka KIMURA  
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pp.414-423  PAPER-Analog Circuits
Low-Voltage Analog Circuit Design Techniques: A Review
Kazuo KATO  
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pp.424-429  PAPER-Analog Circuits
A Monolithic GaAs Linear Power Amplifier Operating with a Single Low 2.7-V Supply for 1.9-GHz Digital Mobile Communication Applications
Masami NAGAOKA  Tomotoshi INOUE  Katsue KAWAKYU  Shuichi OBAYASHI  Hiroyuki KAYANO  Eiji TAKAGI  Yoshikazu TANABE  Misao YOSHIMURA  Kenji ISHIDA  Yoshiaki KITAURA  Naotaka UCHITOMI  
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pp.430-435  PAPER-Analog Circuits
Low-Power Technology for GaAs Front-End ICs
Tadayoshi NAKATSUKA  Junji ITOH  Kazuaki TAKAHASHI  Hiroyuki SAKAI  Makoto TAKEMOTO  Shinji YAMAMOTO  Kazuhisa FUJIMOTO  Morikazu SAGAWA  Osamu ISHIKAWA  
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pp.436-440  PAPER-DA/Architecture
A Method for Reducing Power Consumption of CMOS Logic Based on Signal Transition Probability
Kunihiro ASADA  Junichi AKITA  
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pp.441-446  PAPER-DA/Architecture
Synergistic Power/Area Optimization with Transistor Sizing and Wire Length Minimization
Masaaki YAMADA  Sachiko KUROSAWA  Reiko NOJIMA  Naohito KOJIMA  Takashi MITSUHASHI  Nobuyuki GOTO  
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Regular Section

pp.447-453  PAPER-Opto-Electronics
A Mixed Photonic/Electronic Circuit Simulation Including Transient Noise Sources
Eiichi SANO  Mikio YONEYAMA  
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pp.454-461  PAPER-Electromagnetic Theory
Enhanced Two-Level Optical Resonance in Spherical Microcavities
Kazuya HAYATA  Tsutomu KOSHIDA  Masanori KOSHIBA  
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