IEICE TRANSACTIONS on Electronics

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Volume E77-C No.12  (Publication Date:1994/12/25)
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Special Issue on Multimedia, Analog and Processing LSIs

pp.1847-1848  FOREWORD
FOREWORD
Gensuke GOTO  
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pp.1849-1858  INVITED PAPER-Multimedia System LSIs
Current Status of Future Television System Development
Yuichi NINOMIYA  
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pp.1859-1864  PAPER-Multimedia System LSIs
Development of Improved Low Power MUSE (HDTV) Decoder Chip Set 2.5th Generation MUSE Chip Set
Kiyoshi KOHIYAMA  Kota OTSUBO  Hidenaga TAKAHASHI  Kiyotaka OGAWA  Yukio OTOBE  
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pp.1865-1872  PAPER-Multimedia System LSIs
An Efficient Self-Timed Queue Architecture for ATM Switch LSIs
Harufusa KONDOH  Hideaki YAMANAKA  Masahiko ISHIWAKI  Yoshio MATSUDA  Masao NAKAYA  
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pp.1873-1880  PAPER-Multimedia System LSIs
VLSI Implemented 60 Mb/s QPSK/OQPSK Burst Digital Demodulator for Radio Application
Yoichi MATSUMOTO  Kiyoshi KOBAYASHI  Tetsu SAKATA  Kazuhiko SEKI  Shuji KUBOTA  Shuzo KATO  
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pp.1881-1887  PAPER-Multimedia System LSIs
3-D CG Media Chip: An Experimental Single-Chip Architecture for Three-Dimensional Computer Graphics
Takao WATANABE  Kazushige AYUKAWA  Yoshinobu NAKAGOME  
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pp.1888-1894  PAPER-Multimedia System LSIs
Ultra-High-Speed and Universal-Coding-Rate Viterbi Decoder VLSIC--SNUFEC VLSI--
Katsuhiko KAWAZOE  Shunji HONDA  Shuji KUBOTA  Shuzo KATO  
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pp.1895-1902  INVITED PAPER-Analog LSIs
Evolution of Mixed-Signal Communications LSIs
Masayuki ISHIKAWA  Tsuneo TSUKAHARA  Yukio AKAZAWA  
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pp.1903-1911  PAPER-Analog LSIs
A Video-Rate 10-b Triple-Stage Bi-CMOS A/D Converter
Akira MATSUZAWA  Shoichiro TADA  
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pp.1912-1919  PAPER-Analog LSIs
Digital Correction Technique for Multi-Stage Noise-Shaping with an RC-Analog Integrator
Yasuyuki MATSUYA  Naohiko YUHKI  Yukio AKAZAWA  
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pp.1920-1929  INVITED PAPER-Processors
An Overview of Video Coding VLSIs
Ryota KASAI  Toshihiro MINAMI  
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pp.1930-1936  PAPER-Processors
A Half-Pel Precision Motion Estimation Processor for NTSC-Resolution Video
Shin-ichi URAMOTO  Akihiko TAKABATAKE  Mitsuyoshi SUZUKI  Hiroki SAKURAI  Masahiko YOSHIMOTO  
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pp.1937-1943  PAPER-Processors
Neural Network Multiprocessors Applied with Dynamically Reconfigurable Pipeline Architecture
Takayuki MORISHITA  Iwao TERAMOTO  
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pp.1944-1950  INVITED PAPER-Processor Interfaces
High-Speed, Small-Amplitude I/O Interface Circuits for Memory Bus Application
Masao TAGUCHI  
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pp.1951-1956  PAPER-Processor Interfaces
A PLL-Based Programmable Clock Generator with 50-to 350-MHz Oscillating Range for Video Signal Processors
Junichi GOTO  Masakazu YAMASHINA  Toshiaki INOUE  Benjamin S. SHIH  Youichi KOSEKI  Tadahiko HORIUCHI  Nobuhisa HAMATAKE  Kouichi KUMAGAI  Tadayoshi ENOMOTO  Hachiro YAMADA  
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pp.1957-1965  PAPER-Processor Interfaces
Design of a 3.2 GHz 50 mW 0.5 µm GaAs PLL-Based Clock Generator with 1 V Power Supply
Tadayoshi ENOMOTO  Toshiyuki OKUYAMA  
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Regular Section

pp.1966-1969  PAPER-Semiconductor Materials and Devices
A Novel Effective-Channel-Length/External-Resistance Extraction Method for Small-Geometry MOSFET's
Takaaki YAGI  You-Wen YI  Mitsuchika SAITOH  Nobuo MIKOSHIBA  
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pp.1970-1982  PAPER-Opto-Electronics
Statistical Analysis on Connection Characteristics of Optical Fiber Connectors
Yasuhiro ANDO  Shin'ichi IWANO  Kazunori KANAYAMA  Ryo NAGASE  
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pp.1983-1989  PAPER-Electromagnetic Theory
Electromagnetic Plane Wave Scattering by a Loaded Trough on a Ground Plane
Ryoichi SATO  Hiroshi SHIRAI  
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pp.1990-1992  LETTER-Opto-Electronics
A Beam Adaptive Frame for Finite-Element Beam-Propagation Analysis
Ikuo TAKAKUWA  Akihiro MARUTA  Masanori MATSUHARA  
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