IEICE TRANSACTIONS on Electronics

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Volume E76-C No.5  (Publication Date:1993/05/25)
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Special Section on Low-Power and Low-Voltage Integrated Circuits

pp.671-671  FOREWORD
FOREWORD
Ryota KASAI  
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pp.672-680  INVITED PAPER
Process and Device Technologies of CMOS Devices for Low-Voltage Operation
Masakazu KAKUMU  
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pp.681-686  INVITED PAPER
BiCMOS Circuit Performance at Low Supply Voltage
Yutaka KOBAYASHI  
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pp.687-694  PAPER
A High-Speed Feed-Forward BiNMOS Driver for Low-Voltage LSls
Takakuni DOUSEKI  Shin'ichiro MUTOH  
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pp.695-700  PAPER
BiCMOS Circuit Techniques for 3.3 V Microprocessors
Fumio MURABAYASHI  Tatsumi YAMAUCHI  Masahiro IWAMURA  Takashi HOTTA  Tetsuo NAKANO  Yutaka KOBAYASHI  
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pp.701-707  PAPER
Design Considerations for Low-Voltage Crystal Oscillator Circuit in a 1.8-V Single Chip Microprocessor
Shigeo KUBOKI  Takehiro OHTA  Junichi KONO  Yoji NISHIO  
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pp.708-713  PAPER
High-Speed Circuit Techniques for 1 to 5 V Operating Memories
Tomoaki YABE  
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pp.714-737  PAPER
A Unified Analysis of Four-Quadrant Analog Multipliers Consisting of Emitter and Source-Coupled Transistors Operable on Low Supply Voltage
Katsuji KIMURA  
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pp.738-745  PAPER
A 10 bit 50 MS/s CMOS D/A Converter with 2.7 V Power Supply
Takahiro MIKI  Yasuyuki NAKAMURA  Yoshikazu NISHIKAWA  Keisuke OKADA  Yasutaka HORIBA  
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Special Section on the 1992 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.28, No.4 April 1993)

pp.746-747  FOREWORD
FOREWORD
Charles G. SODINI  Toshiaki MASUHARA  
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pp.748-753  PAPER
Low-Voltage ULSI Design
Katsuhiro SHIMOHIGASHI  Koichi SEKI  
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pp.754-759  PAPER
Sub-1-V Swing Internal Bus Architecture for Future Low-Power ULSI's
Yoshinobu NAKAGOME  Kiyoo ITOH  Masanori ISODA  Kan TAKEUCHI  Masakazu AOKI  
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pp.760-770  PAPER
Experimental Results and Modeling Techniques for Substrate Noise in Mixed-Signal Integrated Circuits
David K. SU  Marc J. LOINAZ  Shoichi MASUI  Bruce A. WOOLEY  
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pp.771-777  PAPER
A CCD/CMOS-Based Imager with Integrated Focal Plane Signal Processing
Craig L. KEAST  Charles G. SODINI  
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pp.778-786  PAPER
A 10-b 300-MHz Interpolated-Parallel A/D Converter
Hiroshi KIMURA  Akira MATSUZAWA  Takashi NAKAMURA  Shigeki SAWADA  
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pp.787-794  PAPER
An 8-b 85-MS/s Parallel Pipeline A/D Converter in 1-µm CMOS
Cormac S. G. CONROY  David W. CLINE  Paul R. GRAY  
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pp.795-801  PAPER
A Low-Power 12-b Analog-to-Digital Converter with On-Chip Precision Trimming
Michiel de WIT  Khen-Sang TAN  Richard K. HESTER  
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pp.802-810  PAPER
A 20-MHz Sixth-Order BiCMOS Parasitic-Insensitive Continuous-Time Filter and Second-Order Equalizer Optimized for Disk-Drive Read Channels
Carlos A. LABER  Paul R. GRAY  
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pp.811-817  PAPER
An Interpolative Bandpass Converter on a 1.2-µm BiCMOS Analog/Digital Array
Gerhard TRÖSTER  Hans-Joachim DREßLER  Hans-Joachim GOLBERG  Werner SCHARDEIN  Edgar ZOCHER  Armin WEDEL  Karl SCHOPPE  Jürgen ARNDT  
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pp.818-823  PAPER
A 6-ns 1-Mb CMOS SRAM with Latched Sense Amplifier
Teruo SEKI  Eisaku ITOH  Chiaki FURUKAWA  Isamu MAENO  Tadashi OZAWA  Hiroyuki SANO  Noriyuki SUZUKI  
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pp.824-829  PAPER
Design Techniques for High-Throughput BiCMOS Self-Timed SRAM's
Koichi YOKOMIZO  Kuniyoshi NAITO  
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pp.830-838  PAPER
A 500-Megabyte/s Data-Rate 4.5M DRAM
Natsuki KUSHIYAMA  Shigeo OHSHIMA  Don STARK  Hiroyuki NOJI  Kiyofumi SAKURAI  Satoru TAKASE  Tohru FURUYAMA  Richard M. BARTH  Andy CHAN  John DILLON  James A. GASBARRO  Matthew M. GRIFFIN  Mark HOROWITZ  Thomas H. LEE  Victor LEE  
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pp.839-843  PAPER
Variable VCC Design Techniques for Battery-Operated DRAM's
Seung-Moon YOO  Ejaz HAQ  Seung-Hoon LEE  Yun-Ho CHOI  Soo-IN CHO  Nam-Soo KANG  Daeje CHIN  
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pp.844-849  PAPER
Low-Power On-Chip Supply Voltage Conversion Scheme for Ultrahigh-Density DRAM's
Daisaburo TAKASHIMA  Shigeyoshi WATANABE  Tsuneaki FUSE  Kazumasa SUNOUCHI  Takahiko HARA  
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pp.850-852  LETTER
Low-Power 1/2 Frequency Dividers Using 0.1-µm CMOS Circuits Built with Ultrathin SIMOX Substrates
M. FUJISHIMA  K. ASADA  Y. OMURA  K. IZUMI  
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pp.853-857  LETTER
A 1-GHz/0.9-mW CMOS/SIMOX Divide-by-128/129 Dual-Modulus Prescaler Using a Divide-by-2/3 Synchronous Counter
Yuichi KADO  Masao SUZUKI  Keiichi KOIKE  Yasuhisa OMURA  Katsutoshi IZUMI  
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pp.858-862  LETTER
A Si Bipolar 1.4-GHz Time Space Switch LSI for B-ISDN
Osamu MATSUDA  Shin-ichiro HAYANO  Takao TAKEUCHI  Hideki KITAHATA  Hisashi TAKEMURA  Tsutomu TASHIRO  
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pp.863-867  LETTER
A Current-Controlled Latch Sense Amplifier and a Static Power-Saving Input Buffer for Low-Power Architecture
Tsuguo KOBAYASHI  Kazutaka NOGAMI  Tsukasa SHIROTORI  Yukihiro FUJIMOTO  
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