IEICE TRANSACTIONS on Electronics

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Volume E75-C No.4  (Publication Date:1992/04/25)
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Joint Special Issue on the 1991 VLSI Circuits Symposium

pp.361-362  FOREWORD
FOREWORD
Akihiko MORINO  Bruce A. WOOLEY  
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pp.363-370  PAPER
Limitations, Innovations, and Challenges of Circuits and Devices into a Half Micrometer and Beyond
Minoru NAGATA  
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pp.371-382  PAPER
Low-Power CMOS Digital Design
Anantha P. CHANDRAKASAN  Samuel SHENG  Robert W. BRODERSEN  
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pp.383-389  PAPER
2.5-V Bipolar/CMOS Circuits for 0.25-µm BiCMOS Technology
Chih-Liang CHEN  
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pp.390-397  PAPER
A 100-MHz 2-D Discrete Cosine Transform Core Processor
Shin-ichi URAMOTO  Yoshitsugu INOUE  Akihiko TAKABATAKE  Jun TAKEDA  Yukihiro YAMASHITA  Hideyuki TERANE  Masahiko YOSHIMOTO  
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pp.398-404  PAPER
Highly Parallel Collision Detection Processor for Intelligent Robots
Michitaka KAMEYAMA  Tadao AMADA  Tatsuo HIGUCHI  
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pp.405-412  PAPER
Fault-Tolerant Architecture in a Cache Memory Control LSI
Yasushi OOI  Masahiko KASHIMURA  Hidenori TAKEUCHI  Eiji KAWAMURA  
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pp.413-427  PAPER
A Family of User-Programmable Peripherals with a Functional Unit Architecture
Alexander S. SHUBAT  Cuong Q. TRINH  Arkady ZALIZNYAK  Arye ZIKLIK  Anirban ROY  Reza KAZEROUNIAN  Y. CEDAR  Boaz EITAN  
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pp.428-436  PAPER
A 250-Mb/s, 700-mW, 32-Highway 8-b S/P Converter LSI with Cross-Access Memory
Yusuke OHTOMO  Masao SUZUKI  
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pp.437-442  PAPER
A CMOS Line Driver with 80-dB Linearity for ISDN Applications
Haideh KHORRAMABADI  
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pp.443-451  PAPER
CMOS Resistive Fuses for Image Smoothing and Segmentation
Paul C. YU  Steven J. DECKER  Hae-Seung LEE  Charles G. SODINI  John L. WYATT,Jr.  
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pp.452-460  PAPER
A Design Technique for a High-Gain, 10-GHz Class-Bandwidth GaAs MESFET Amplifier IC Module
Noboru ISHIHARA  Eiichi SANO  Yuhki IMAI  Hiroyuki KIKUCHI  Yasuro YAMANE  
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pp.461-466  PAPER
An Enhanced Fully Differential Folded-Cascode Op Amp
Katsufumi NAKAMURA  L. Richard CARLEY  
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pp.467-471  PAPER
A Dual-Mode Sensing Scheme of Capacitor-Coupled EEPROM Cell
Masanori HAYASHIKOSHI  Hideto HIDAKA  Kazutami ARIMOTO  Kazuyasu FUJISHIMA  
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pp.472-480  PAPER
A 512-kb Flash EEPROM Embedded in a 32-b Microcontroller
Clinton KUO  Mark WEIDNER  Thomas TOMS  Henry CHOE  Ko-Min CHANG  Ann HARWOOD  Joseph JELEMENSKY  Philip SMITH  
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pp.481-486  PAPER
A New Erasing and Row Decoding Scheme for Low Supply Voltage Operation 16-Mb/64-Mb Flash Memories
Yoshikazu MIYAWAKI  Takeshi NAKAYAMA  Shin-ichi KOBAYASHI  Natsuo AJIKA  Makoto OHI  Yasushi TERADA  Hideaki ARIMA  Tsutomu YOSHIHARA  
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pp.487-494  PAPER
Deep-Submicrometer BiCMOS Circuit Technology for Sub-10-ns ECL 4-Mb DRAM's
Takayuki KAWAHARA  Yoshiki KAWAJIRI  Goro KITSUKAWA  Kazuhiko SAGARA  Yoshifumi KAWAMOTO  Takesada AKIBA  Shisei KATO  Yasushi KAWASE  Kiyoo ITOH  
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pp.495-500  PAPER
Cell-Plate Line Connecting Complementary Bit-Line (C3) Architecture for Battery-Operating DRAM's
Mikio ASAKURA  Kazutami ARIMOTO  Hideto HIDAKA  Kazuyasu FUJISHIMA  
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pp.501-507  PAPER
Word-Line Architecture for Highly Reliable 64-Mb DRAM
Daisaburo TAKASHIMA  Yukihito OOWAKI  Ryu OGIWARA  Yohji WATANABE  Kenji TSUCHIDA  Masako OHTA  Hiroaki NAKANO  Shigeyoshi WATANABE  Kazunori OHUCHI  
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pp.508-515  PAPER
A High-Density Dual-Port Memory Cell Operation and Array Architecture for ULSI DRAM's
Hideto HIDAKA  Kazutami ARIMOTO  Kazuyasu FUJISHIMA  
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pp.516-523  PAPER
A High-Speed Sensing Scheme for 1T Dynamic RAM's Utilizing the Clamped Bit-Line Sense Amplifier
Travis N. BLALOCK  Richard C. JAEGER  
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pp.524-529  PAPER
Temperature-Compensation Circuit Techniques for High-Density CMOS DRAM's
Dong-Sun MIN  Sooin CHO  Dong Soo JUN  Dong-Jae LEE  Yongsik SEOK  Daeje CHIN  
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pp.530-538  PAPER
High-Speed Sensing Techniques for Ultrahigh-Speed SRAM's
Hiroaki NAMBU  Kazuo KANETANI  Youji IDEI  Noriyuki HOMMA  Kunihiko YAMAGUCHI  Toshirou HIRAMOTO  Nobuo TAMBA  Masanori ODAKA  Kunihiko WATANABE  Takahide IKEDA  Kenichi OHHATA  Yoshiaki SAKURAI  
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pp.539-546  PAPER
Automated Bias Control (ABC) Circuit for High-Performance VLSI's
Tadahiro KURODA  Toshiyuki FUKUNAGA  Kenji MATSUO  Kazuhiko KASAI  Ayako HIRATA  Shinji FUJII  Masahiro KIMURA  Hiroaki SUZUKI  
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pp.547-554  PAPER
A 576K 3.5-ns Access BiCMOS ECL Static RAM with Array Built-in Self-Test
Henry A. BONGES,  R. Dean ADAMS  Archibald J. ALLEN  Roy FLAKER  Kenneth S. GRAY  Erik L. HEDBERG  W. Timothy HOLMAN  George M. LATTIMORE  David A. LAVALETTE  Kim Yen T. NGUYEN  Alan L. ROBERTS  
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pp.555-557  LETTER
An 8.5-ns 112-b Transmission Gate Adder with a Conflict-Free Bypass Circuit
T. SATO  M. SAKATE  H. OKADA  T. SUKEMURA  G. GOTO  
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pp.558-561  LETTER
High-Speed Low-Power AC-Coupled Complementary Push-Pull ECL Circuit
C. T. CHUANG  D. D. TANG  
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pp.562-565  LETTER
A Si Bipolar 5-Gb/s 8:1 Multiplexer and 4.2-Gb/s 1:8 Demultiplexer
M. OHUCHI  T. OKAMURA  A. SAWAIRI  F. KUNIBA  K. MATSUMOTO  T. TASHIRO  S. HATAKEYAMA  K. OKUYAMA  
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pp.566-568  LETTER
Multigigahertz Voltage-Controlled Oscillators in Advanced Silicon Bipolar Technology
Mehmet SOYUER  James D. WARNOCK  
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pp.569-571  LETTER
High-Speed CMOS I/O Buffer Circuits
Manabu ISHIBE  Shoji OTAKA  Junichi TAKEDA  Shigeru TANAKA  Yoshiaki TOYOSHIMA  Satoru TAKATSUKA  Shoichi SHIMIZU  
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pp.572-575  LETTER
A 1.7-V Adjustable I/O Interface for Low-Voltage Fast SRAM's
Koichiro ISHIBASHI  Katsuro SASAKI  Toshiaki YAMANAKA  Hiroshi TOYOSHIMA  Fumio KOJIMA  
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pp.576-580  LETTER
A Pulsed Sensing Scheme with a Limited Bit-Line Swing
R. E. SCHEUERLEIN  Y. KATAYAMA  T. KIRIHATA  Y. SAKAUE  A. SATOH  T. SUNAGA  T. YOSHIKAWA  K. KITAMURA  S. H. DHONG  
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pp.581-583  LETTER
Consideration of Poly-Si Loaded Cell Capacity Limits for Low-Power and High-Speed SRAM's
H. KATO  K. SATO  M. MATSUI  H. SHIBATA  K. HASHIMOTO  T. OOTANI  K. OCHII  
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