IEICE TRANSACTIONS on Electronics

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Volume E74-C No.4  (Publication Date:1991/04/25)
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Special Issue on LSI Memories

pp.797-798  FOREWORD
FOREWORD
Shoji HORIGUCHI  
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pp.799-811  INVITED PAPER-DRAM
Reviews and Prospects of DRAM Technology
Yoshinobu NAKAGOME  Kiyoo ITOH  
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pp.812-817  PAPER-DRAM
Leakage Current Reduction in Surrounding Hi-Capacitor DRAM Cell
Geshu FUSE  Ichirou NAKAO  Yohei ICHIKAWA  Chiaki KUDO  Toshiki YABU  Akito UNO  Kazuyuki SAWADA  Yasushi NAITO  Michihiro INOUE  Hiroshi IWASAKI  
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pp.818-826  PAPER-DRAM
Double Self-Aligned Contact Technology for Shielded Bit Line Type Stacked Capacitor Cell of 16 MDRAM
Masanori FUKUMOTO  Yasushi NAITO  Kazuhiro MATSUYAMA  Hisashi OGAWA  Koji MATSUOKA  Takashi HORI  Hiroyuki SAKAI  Ichiro NAKAO  Hisakazu KOTANI  Hiroshi IWASAKI  Michihiro INOUE  
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pp.827-838  INVITED PAPER-SRAM
Reviews and Prospects of SRAM Technology
Masahide TAKADA  Tadayoshi ENOMOTO  
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pp.839-844  PAPER-SRAM
Alpha-Particle-Induced Charge Amplification by Parasitic npn Transistor in Ultra-High-Speed Bipolar RAMs
Hiroaki NAMBU  Youji IDEI  Kazuo KANETANI  Kunihiko YAMAGUCHI  Noriyuki HOMMA  Kenichi OHHATA  Yoshiaki SAKURAI  
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pp.845-852  PAPER-SRAM
Logic Functional Level Converter for High Speed Address Decoder of ECL I/O BiCMOS SRAMs
Kazuyuki NAKAMURA  Masahide TAKADA  Toshio TAKESHIMA  Kouichirou FURUTA  Tohru YAMAZAKI  Kiyotaka IMAI  Susumu OHI  Yumi SEKINE  Yukio MINATO  Hisamitsu KIMOTO  
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pp.853-858  PAPER-SRAM
A New Soft-Error Phenomenon is ULSI SRAM's--Inverted Dependence of Soft-Error Rate on Cycle Time--
Shuji MURAKAMI  Tomohisa WADA  Masanao EINO  Motomu UKITA  Yasumasa NISHIMURA  Kimio SUZUKI  Kenji ANAMI  
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pp.859-867  PAPER-SRAM
Design of 4K 1-bit Josephson RAM Using Capacitively Coupled Cells
Hideo SUZUKI  Shinya HASUO  
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pp.868-874  INVITED PAPER-ROM
Reviews and Prospects of Non-Volatile Semiconductor Memories
Fujio MASUOKA  Riichiro SHIROTA  Koji SAKUI  
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pp.875-884  PAPER-ROM
Tunnel Oxide Thickness Optimization for High-Performance MNOS Nonvolatile Memory Devices
Shin-ichi MINAMI  Yoshiaki KAMIGAKI  
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pp.885-889  PAPER-ROM
Low Detecting Bias and Its Influence on Non-volatile Memory Data Access
Shoji KITAZAWA  Teruhiro HARADA  
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pp.890-895  PAPER-ROM
A 26 ns 1 Mbit CMOS Mask ROM
Yasuhiro HOTTA  Mikiro OKADA  Ryusuke MATSUYAMA  Hiroshi TSUGITA  Kenji SANO  Akihiko KUNIKANE  
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pp.896-901  PAPER-ROM
An 85 ns 16 Mb CMOS EPROM
Misao HIGUCHI  Takahiko URAI  Kazuhisa NINOMIYA  Takeshi WATANABE  Shoji KOYAMA  Toshikatsu JINBO  Takeshi OKAZAWA  
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pp.902-908  INVITED PAPER-ASIC
Reviews and Prospects of ASIC Memories
Junzo YAMADA  
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pp.909-917  PAPER-ASIC
A 4096-Channel Time-Switch LSI with Switching Address Protection
Yusuke OHTOMO  Tadanobu NIKAIDO  Masaharu KAWAKAMI  Yasuyuki GOTO  
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pp.918-928  PAPER-ASIC
A Design of a High-Density Multi-Level Matching Array Chip for Associative Processing
Takahiro HANYU  Hiroto ISHII  Tatsuo HIGUCHI  
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pp.929-937  PAPER-ASIC
A 5 ns 369 kbit Port-Configurable Embedded SRAM with 0.5 µm CMOS Gate Array
Kazuhiro SAWADA  Toshinari TAKAYANAGI  Kazutaka NOGAMI  Makoto TAKAHASHI  Masanori UCHIDA  Yukiko ITOH  Tetsuya IIZUKA  
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pp.938-945  PAPER-ASIC
Hierarchical Module Generation Technique for a High Performance Memory Macrocell
Shigeru DATE  Ken-ichi ENDO  Mitsuyoshi NAGATANI  Junzo YAMADA  
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Regular Section

pp.946-950  PAPER-Quantum Electronics
Second Harmonic Generation from Mixtures of Organic Nonlinear Materials MNA and pNA
Ding Yu CHEN  Naomichi OKAMOTO  Tohru SASAKI  Shigeru TASAKA  Ryoka MATSUSHIMA  
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pp.951-954  LETTER-Recording and Memory Technologies
High Speed, Large Capacity Optical Disk Using Pit-Edge Recording and MCAV Method
Takeshi MAEDA  Atushi SAITO  Hisataka SUGIYAMA  Shinichi ARAI  Kazuo SHIGEMATSU  
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