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IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences

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Online ISSN : 1745-1337

Volume E94-A No.12 (Publication Date:2011/12/01)

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Special Section on VLSI Design and CAD Algorithms

pp.2481-2481 FOREWORD FOREWORD Atsushi TAKAHASHI
	Summary \| Full Text:PDF (114.2KB)

pp.2482-2489 PAPER-Physical Level Design Greedy Algorithm for the On-Chip Decoupling Capacitance Optimization to Satisfy the Voltage Drop Constraint Mikiko SODE TANAKA Nozomu TOGAWA Masao YANAGISAWA Satoshi GOTO
	Summary \| Full Text:PDF (710.8KB)

pp.2490-2498 PAPER-Physical Level Design Leakage-Aware TSV-Planning with Power-Temperature-Delay Dependence in 3D ICs Kan WANG Sheqin DONG Yuchun MA Yu WANG Xianlong HONG Jason CONG
	Summary \| Full Text:PDF (2.8MB)

pp.2499-2509 PAPER-Physical Level Design Sleep Transistor Sizing Method Using Accurate Delay Estimation Considering Input Vector Pattern and Non-linear Current Model Seidai TAKEDA Kyundong KIM Hiroshi NAKAMURA Kimiyoshi USAMI
	Summary \| Full Text:PDF (2MB)

pp.2510-2518 PAPER-Physical Level Design Single-Layer Trunk Routing Using Minimal 45-Degree Lines Kyosuke SHINODA Yukihide KOHIRA Atsushi TAKAHASHI
	Summary \| Full Text:PDF (1.4MB)

pp.2519-2527 PAPER-Physical Level Design Low Power Placement and Routing for the Coarse-Grained Power Gating FPGA Architecture Ce LI Yiping DONG Takahiro WATANABE
	Summary \| Full Text:PDF (7.7MB)

pp.2528-2536 PAPER-Device and Circuit Modeling and Analysis A Statistical Maximum Algorithm for Gaussian Mixture Models Considering the Cumulative Distribution Function Curve Shuji TSUKIYAMA Masahiro FUKUI
	Summary \| Full Text:PDF (1.1MB)

pp.2537-2544 PAPER-Device and Circuit Modeling and Analysis Extracting Device-Parameter Variations with RO-Based Sensors Ken-ichi SHINKAI Masanori HASHIMOTO Takao ONOYE
	Summary \| Full Text:PDF (1016.9KB)

pp.2545-2553 PAPER-Device and Circuit Modeling and Analysis Stress Probability Computation for Estimating NBTI-Induced Delay Degradation Hiroaki KONOURA Yukio MITSUYAMA Masanori HASHIMOTO Takao ONOYE
	Summary \| Full Text:PDF (1.4MB)

pp.2554-2562 PAPER-Device and Circuit Modeling and Analysis A 65-nm CMOS Fully Integrated Shock-Wave Antenna Array with On-Chip Jitter and Pulse-Delay Adjustment for Millimeter-Wave Active Imaging Application Nguyen Ngoc MAI KHANH Masahiro SASAKI Kunihiro ASADA
	Summary \| Full Text:PDF (4.4MB)

pp.2563-2570 PAPER-Logic Synthesis, Test and Verification Flexible Test Scheduling for an Asynchronous On-Chip Interconnect through Special Data Transfer Tsuyoshi IWAGAKI Eiri TAKEDA Mineo KANEKO
	Summary \| Full Text:PDF (1.3MB)

pp.2571-2578 PAPER-Logic Synthesis, Test and Verification Hybrid Test Application in Partial Skewed-Load Scan Design Yuki YOSHIKAWA Tomomi NUWA Hideyuki ICHIHARA Tomoo INOUE
	Summary \| Full Text:PDF (782.7KB)

pp.2579-2586 PAPER-Logic Synthesis, Test and Verification Multi-Operand Adder Synthesis Targeting FPGAs Taeko MATSUNAGA Shinji KIMURA Yusuke MATSUNAGA
	Summary \| Full Text:PDF (718.5KB)

pp.2587-2596 PAPER-High-Level Synthesis and System-Level Design A 6.72-Gb/s 8 pJ/bit/iteration IEEE 802.15.3c LDPC Decoder Chip Zhixiang CHEN Xiao PENG Xiongxin ZHAO Leona OKAMURA Dajiang ZHOU Satoshi GOTO
	Summary \| Full Text:PDF (1.6MB)

pp.2597-2608 PAPER-High-Level Synthesis and System-Level Design Implementation of Stack Data Placement and Run Time Management Using a Scratch-Pad Memory for Energy Consumption Reduction of Embedded Applications Lovic GAUTHIER Tohru ISHIHARA
	Summary \| Full Text:PDF (1.9MB)

pp.2609-2618 PAPER-High-Level Synthesis and System-Level Design A 98 GMACs/W 32-Core Vector Processor in 65 nm CMOS Xun HE Xin JIN Minghui WANG Dajiang ZHOU Satoshi GOTO
	Summary \| Full Text:PDF (3.6MB)

pp.2619-2627 PAPER-High-Level Synthesis and System-Level Design Iterative Synthesis Methods Estimating Programmable-Wire Congestion in a Dynamically Reconfigurable Processor Takao TOI Takumi OKAMOTO Toru AWASHIMA Kazutoshi WAKABAYASHI Hideharu AMANO
	Summary \| Full Text:PDF (2.1MB)

pp.2628-2638 PAPER-High-Level Synthesis and System-Level Design Compact Architecture for ASIC and FPGA Implementation of the KASUMI Block Cipher Dai YAMAMOTO Kouichi ITOH Jun YAJIMA
	Summary \| Full Text:PDF (945.6KB)

pp.2639-2648 PAPER-High-Level Synthesis and System-Level Design A New Recovery Mechanism in Superscalar Microprocessors by Recovering Critical Misprediction Jiongyao YE Yu WAN Takahiro WATANABE
	Summary \| Full Text:PDF (744KB)

pp.2649-2658 PAPER-High-Level Synthesis and System-Level Design Maximal Interconnect Resilient Methodology for Fault Tolerance, Yield, and Reliability Improvement in Network on Chip Katherine Shu-Min LI Chih-Yun PAI Liang-Bi CHEN
	Summary \| Full Text:PDF (1.9MB)

pp.2659-2668 PAPER-High-Level Synthesis and System-Level Design Two-Stage Configurable Decoder Model for Domain Specific FEC Decoder Design Ittetsu TANIGUCHI Ayataka KOBAYASHI Keishi SAKANUSHI Yoshinori TAKEUCHI Masaharu IMAI
	Summary \| Full Text:PDF (1020.2KB)

pp.2669-2675 PAPER-High-Level Synthesis and System-Level Design Variation-Tolerance of a 65-nm Error-Hardened Dual-Modular-Redundancy Flip-Flop Measured by Shift-Register-Based Monitor Structures Chikara HAMANAKA Ryosuke YAMAMOTO Jun FURUTA Kanto KUBOTA Kazutoshi KOBAYASHI Hidetoshi ONODERA
	Summary \| Full Text:PDF (3.1MB)

pp.2676-2684 PAPER-Circuit Design A High-Efficiency On-Chip DC-DC Down-Conversion Using Selectable Supply-Voltage Charge-Recycling Byung-Do YANG
	Summary \| Full Text:PDF (1.4MB)

pp.2685-2692 PAPER-Circuit Design A High Efficiency Hybrid Step-Up/Step-Down DC-DC Converter Using Digital Dither for Smooth Transition Yanzhao MA Hongyi WANG Guican CHEN
	Summary \| Full Text:PDF (887.1KB)

pp.2693-2700 PAPER-Circuit Design 7T SRAM Enabling Low-Energy Instantaneous Block Copy and Its Application to Transactional Memory Shunsuke OKUMURA Yuki KAGIYAMA Yohei NAKATA Shusuke YOSHIMOTO Hiroshi KAWAGUCHI Masahiko YOSHIMOTO
	Summary \| Full Text:PDF (3.2MB)

pp.2701-2708 PAPER-Circuit Design A Low-Power Multi-Phase Oscillator with Transfer Gate Phase Coupler Enabling Even-Numbered Phase Output Toshihiro KONISHI Hyeokjong LEE Shintaro IZUMI Takashi TAKEUCHI Masahiko YOSHIMOTO Hiroshi KAWAGUCHI
	Summary \| Full Text:PDF (3MB)

Special Section on Wideband Systems

pp.2709-2709 FOREWORD FOREWORD Makoto ITAMI
	Summary \| Full Text:PDF (84KB)

pp.2710-2718 PAPER Effective Transmit Weight Design for DPC with Maximum Beam in Multiuser MIMO OFDM Downlink Cong LI Yasunori IWANAMI
	Summary \| Full Text:PDF (790.8KB)

pp.2719-2727 PAPER Open Loop DPC Beamforming Effective for Multiuser MIMO Transmissions in FDD Systems Tomoko MATSUMOTO Yasuyuki HATAKAWA Satoshi KONISHI
	Summary \| Full Text:PDF (795.7KB)

pp.2728-2736 PAPER Orthogonal and ZCZ Sets of Real-Valued Periodic Orthogonal Sequences from Huffman Sequences Takahiro MATSUMOTO Shinya MATSUFUJI Tetsuya KOJIMA Udaya PARAMPALLI
	Summary \| Full Text:PDF (487.4KB)

pp.2737-2745 PAPER A Tracking System Using a Differential Detector for M-ary Bi-orthogonal Spread Spectrum Communication Systems Junya KAWATA Kouji OHUCHI Hiromasa HABUCHI
	Summary \| Full Text:PDF (950KB)

pp.2746-2752 PAPER Multi-User Scheduling Method Considering Fairness and Mitigation of Multi-Cell Interference for Multi-Hop Cellular System Yuji OKAMOTO Takeo FUJII
	Summary \| Full Text:PDF (1.2MB)

pp.2753-2761 PAPER BER Evaluation of CDMA-Based Wireless Services Transmission over Aperture Averaged FSO Links Chedlia BEN NAILA Kazuhiko WAKAMORI Mitsuji MATSUMOTO
	Summary \| Full Text:PDF (1.4MB)

pp.2762-2772 PAPER Interference Mitigation Capability of a Low Duty DS-Multiband-UWB System in Realistic Environment Chin-Sean SUM Shigenobu SASAKI Hiroshi HARADA
	Summary \| Full Text:PDF (832.6KB)

pp.2773-2775 LETTER Power Supply Overlaid Communication with Common Clock Delivery for Cooperative Motion Control Fumikazu MINAMIYAMA Hidetsugu KOGA Kentaro KOBAYASHI Masaaki KATAYAMA
	Summary \| Full Text:PDF (610.5KB)

pp.2776-2779 LETTER Subcarrier Mapping for Single-User SC-FDMA Relay Communications Yu HEMMI Koichi ADACHI Tomoaki OHTSUKI
	Summary \| Full Text:PDF (832.3KB)

pp.2780-2786 LETTER Iterations of FB-MSDSD and Turbo Codes over the Correlated Flat Fading Channel Chien-Sheng CHEN Ching-Chi LO
	Summary \| Full Text:PDF (896.7KB)

Special Section on Mathematical Systems Science and its Applications

pp.2787-2787 FOREWORD FOREWORD Toshimitsu USHIO
	Summary \| Full Text:PDF (91.8KB)

pp.2788-2793 PAPER-INVITED A Verification and Analysis Tool Set for Embedded System Design Yuichi NAKAMURA
	Summary \| Full Text:PDF (1.7MB)

pp.2794-2801 PAPER Checking On-the-Fly Universality and Inclusion Problems of Visibly Pushdown Automata Nguyen VAN TANG Hitoshi OHSAKI
	Summary \| Full Text:PDF (879.8KB)

pp.2802-2809 PAPER Decentralized Supervisory Control of Timed Discrete Event Systems Masashi NOMURA Shigemasa TAKAI
	Summary \| Full Text:PDF (848.3KB)

pp.2810-2820 PAPER Option-Based Monte Carlo Algorithm with Conditioned Updating to Learn Conflict-Free Task Allocation in Transport Applications Alex VALDIVIELSO Toshiyuki MIYAMOTO
	Summary \| Full Text:PDF (961.4KB)

pp.2821-2829 PAPER Polynomial Time Verification of Behavioral Inheritance for Interworkflows Based on WfMC Protocol Shingo YAMAGUCHI Tomohiro HIRAKAWA
	Summary \| Full Text:PDF (482.4KB)

pp.2830-2831 LETTER Simplified Relative Model to Measure Visual Fatigue in a Stereoscopy Jae Gon KIM Jun-Dong CHO
	Summary \| Full Text:PDF (797.7KB)

pp.2832-2835 LETTER Verifying Structurally Weakly Persistent Net Is Co-NP Complete Atsushi OHTA Kohkichi TSUJI
	Summary \| Full Text:PDF (140.3KB)

Regular Section

pp.2836-2844 PAPER-Digital Signal Processing Flicker Parameters Estimation in Old Film Sequences Containing Moving Objects Xiaoyong ZHANG Masahide ABE Masayuki KAWAMATA
	Summary \| Full Text:PDF (1.4MB)

pp.2845-2852 PAPER-Nonlinear Problems Self-Organizing Digital Spike Maps for Learning of Spike-Trains Takashi OGAWA Toshimichi SAITO
	Summary \| Full Text:PDF (1.4MB)

pp.2853-2865 PAPER-VLSI Design Technology and CAD On Structural Analysis and Efficiency for Graph-Based Rewiring Techniques Fu-Shing CHIM Tak-Kei LAM Yu-Liang WU Hongbing FAN
	Summary \| Full Text:PDF (862.2KB)

pp.2866-2873 PAPER-Reliability, Maintainability and Safety Analysis Adaptive Go-Back-N ARQ Protocol over Two Parallel Channels with Slow State Transition Chun-Xiang CHEN Kenichi NAGAOKA Masaharu KOMATSU
	Summary \| Full Text:PDF (459.3KB)

pp.2874-2878 PAPER-Cryptography and Information Security New Constructions of Binary Sequences with Good Autocorrelation Based on Interleaving Technique Xiuwen MA Qiaoyan WEN Jie ZHANG Xuan ZHANG
	Summary \| Full Text:PDF (345.7KB)

pp.2879-2885 PAPER-General Fundamentals and Boundaries Approximate Bayesian Estimation of Varying Binomial Process Kazuho WATANABE Masato OKADA
	Summary \| Full Text:PDF (293.7KB)

pp.2886-2888 LETTER-Systems and Control On the Monotonic Condition for Schur Stability of Real Polynomials Younseok CHOO Gin-Kyu CHOI
	Summary \| Full Text:PDF (66.4KB)

pp.2889-2893 LETTER-Cryptography and Information Security Audio Watermarking Robust against Playback Speed Modification Lili LI Xiangzhong FANG
	Summary \| Full Text:PDF (302.1KB)

pp.2894-2899 LETTER-Coding Theory Simultaneous Code/Error-Trellis Reduction for Convolutional Codes Using Shifted Code/Error-Subsequences Masato TAJIMA Koji OKINO Takashi MIYAGOSHI
	Summary \| Full Text:PDF (247.7KB)