IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences

Archive Index

Online ISSN : 1745-1337
Volume E94-A No.12  (Publication Date:2011/12/01)
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Special Section on VLSI Design and CAD Algorithms

pp.2481-2481  FOREWORD
FOREWORD
Atsushi TAKAHASHI  
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pp.2482-2489  PAPER-Physical Level Design
Greedy Algorithm for the On-Chip Decoupling Capacitance Optimization to Satisfy the Voltage Drop Constraint
Mikiko SODE TANAKA  Nozomu TOGAWA  Masao YANAGISAWA  Satoshi GOTO  
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pp.2490-2498  PAPER-Physical Level Design
Leakage-Aware TSV-Planning with Power-Temperature-Delay Dependence in 3D ICs
Kan WANG  Sheqin DONG  Yuchun MA  Yu WANG  Xianlong HONG  Jason CONG  
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pp.2499-2509  PAPER-Physical Level Design
Sleep Transistor Sizing Method Using Accurate Delay Estimation Considering Input Vector Pattern and Non-linear Current Model
Seidai TAKEDA  Kyundong KIM  Hiroshi NAKAMURA  Kimiyoshi USAMI  
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pp.2510-2518  PAPER-Physical Level Design
Single-Layer Trunk Routing Using Minimal 45-Degree Lines
Kyosuke SHINODA  Yukihide KOHIRA  Atsushi TAKAHASHI  
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pp.2519-2527  PAPER-Physical Level Design
Low Power Placement and Routing for the Coarse-Grained Power Gating FPGA Architecture
Ce LI  Yiping DONG  Takahiro WATANABE  
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pp.2528-2536  PAPER-Device and Circuit Modeling and Analysis
A Statistical Maximum Algorithm for Gaussian Mixture Models Considering the Cumulative Distribution Function Curve
Shuji TSUKIYAMA  Masahiro FUKUI  
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pp.2537-2544  PAPER-Device and Circuit Modeling and Analysis
Extracting Device-Parameter Variations with RO-Based Sensors
Ken-ichi SHINKAI  Masanori HASHIMOTO  Takao ONOYE  
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pp.2545-2553  PAPER-Device and Circuit Modeling and Analysis
Stress Probability Computation for Estimating NBTI-Induced Delay Degradation
Hiroaki KONOURA  Yukio MITSUYAMA  Masanori HASHIMOTO  Takao ONOYE  
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pp.2554-2562  PAPER-Device and Circuit Modeling and Analysis
A 65-nm CMOS Fully Integrated Shock-Wave Antenna Array with On-Chip Jitter and Pulse-Delay Adjustment for Millimeter-Wave Active Imaging Application
Nguyen Ngoc MAI KHANH  Masahiro SASAKI  Kunihiro ASADA  
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pp.2563-2570  PAPER-Logic Synthesis, Test and Verification
Flexible Test Scheduling for an Asynchronous On-Chip Interconnect through Special Data Transfer
Tsuyoshi IWAGAKI  Eiri TAKEDA  Mineo KANEKO  
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pp.2571-2578  PAPER-Logic Synthesis, Test and Verification
Hybrid Test Application in Partial Skewed-Load Scan Design
Yuki YOSHIKAWA  Tomomi NUWA  Hideyuki ICHIHARA  Tomoo INOUE  
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pp.2579-2586  PAPER-Logic Synthesis, Test and Verification
Multi-Operand Adder Synthesis Targeting FPGAs
Taeko MATSUNAGA  Shinji KIMURA  Yusuke MATSUNAGA  
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pp.2587-2596  PAPER-High-Level Synthesis and System-Level Design
A 6.72-Gb/s 8 pJ/bit/iteration IEEE 802.15.3c LDPC Decoder Chip
Zhixiang CHEN  Xiao PENG  Xiongxin ZHAO  Leona OKAMURA  Dajiang ZHOU  Satoshi GOTO  
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pp.2597-2608  PAPER-High-Level Synthesis and System-Level Design
Implementation of Stack Data Placement and Run Time Management Using a Scratch-Pad Memory for Energy Consumption Reduction of Embedded Applications
Lovic GAUTHIER  Tohru ISHIHARA  
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pp.2609-2618  PAPER-High-Level Synthesis and System-Level Design
A 98 GMACs/W 32-Core Vector Processor in 65 nm CMOS
Xun HE  Xin JIN  Minghui WANG  Dajiang ZHOU  Satoshi GOTO  
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pp.2619-2627  PAPER-High-Level Synthesis and System-Level Design
Iterative Synthesis Methods Estimating Programmable-Wire Congestion in a Dynamically Reconfigurable Processor
Takao TOI  Takumi OKAMOTO  Toru AWASHIMA  Kazutoshi WAKABAYASHI  Hideharu AMANO  
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pp.2628-2638  PAPER-High-Level Synthesis and System-Level Design
Compact Architecture for ASIC and FPGA Implementation of the KASUMI Block Cipher
Dai YAMAMOTO  Kouichi ITOH  Jun YAJIMA  
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pp.2639-2648  PAPER-High-Level Synthesis and System-Level Design
A New Recovery Mechanism in Superscalar Microprocessors by Recovering Critical Misprediction
Jiongyao YE  Yu WAN  Takahiro WATANABE  
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pp.2649-2658  PAPER-High-Level Synthesis and System-Level Design
Maximal Interconnect Resilient Methodology for Fault Tolerance, Yield, and Reliability Improvement in Network on Chip
Katherine Shu-Min LI  Chih-Yun PAI  Liang-Bi CHEN  
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pp.2659-2668  PAPER-High-Level Synthesis and System-Level Design
Two-Stage Configurable Decoder Model for Domain Specific FEC Decoder Design
Ittetsu TANIGUCHI  Ayataka KOBAYASHI  Keishi SAKANUSHI  Yoshinori TAKEUCHI  Masaharu IMAI  
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pp.2669-2675  PAPER-High-Level Synthesis and System-Level Design
Variation-Tolerance of a 65-nm Error-Hardened Dual-Modular-Redundancy Flip-Flop Measured by Shift-Register-Based Monitor Structures
Chikara HAMANAKA  Ryosuke YAMAMOTO  Jun FURUTA  Kanto KUBOTA  Kazutoshi KOBAYASHI  Hidetoshi ONODERA  
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pp.2676-2684  PAPER-Circuit Design
A High-Efficiency On-Chip DC-DC Down-Conversion Using Selectable Supply-Voltage Charge-Recycling
Byung-Do YANG  
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pp.2685-2692  PAPER-Circuit Design
A High Efficiency Hybrid Step-Up/Step-Down DC-DC Converter Using Digital Dither for Smooth Transition
Yanzhao MA  Hongyi WANG  Guican CHEN  
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pp.2693-2700  PAPER-Circuit Design
7T SRAM Enabling Low-Energy Instantaneous Block Copy and Its Application to Transactional Memory
Shunsuke OKUMURA  Yuki KAGIYAMA  Yohei NAKATA  Shusuke YOSHIMOTO  Hiroshi KAWAGUCHI  Masahiko YOSHIMOTO  
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pp.2701-2708  PAPER-Circuit Design
A Low-Power Multi-Phase Oscillator with Transfer Gate Phase Coupler Enabling Even-Numbered Phase Output
Toshihiro KONISHI  Hyeokjong LEE  Shintaro IZUMI  Takashi TAKEUCHI  Masahiko YOSHIMOTO  Hiroshi KAWAGUCHI  
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Special Section on Wideband Systems

pp.2709-2709  FOREWORD
FOREWORD
Makoto ITAMI  
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pp.2710-2718  PAPER
Effective Transmit Weight Design for DPC with Maximum Beam in Multiuser MIMO OFDM Downlink
Cong LI  Yasunori IWANAMI  
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pp.2719-2727  PAPER
Open Loop DPC Beamforming Effective for Multiuser MIMO Transmissions in FDD Systems
Tomoko MATSUMOTO  Yasuyuki HATAKAWA  Satoshi KONISHI  
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pp.2728-2736  PAPER
Orthogonal and ZCZ Sets of Real-Valued Periodic Orthogonal Sequences from Huffman Sequences
Takahiro MATSUMOTO  Shinya MATSUFUJI  Tetsuya KOJIMA  Udaya PARAMPALLI  
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pp.2737-2745  PAPER
A Tracking System Using a Differential Detector for M-ary Bi-orthogonal Spread Spectrum Communication Systems
Junya KAWATA  Kouji OHUCHI  Hiromasa HABUCHI  
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pp.2746-2752  PAPER
Multi-User Scheduling Method Considering Fairness and Mitigation of Multi-Cell Interference for Multi-Hop Cellular System
Yuji OKAMOTO  Takeo FUJII  
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pp.2753-2761  PAPER
BER Evaluation of CDMA-Based Wireless Services Transmission over Aperture Averaged FSO Links
Chedlia BEN NAILA  Kazuhiko WAKAMORI  Mitsuji MATSUMOTO  
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pp.2762-2772  PAPER
Interference Mitigation Capability of a Low Duty DS-Multiband-UWB System in Realistic Environment
Chin-Sean SUM  Shigenobu SASAKI  Hiroshi HARADA  
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pp.2773-2775  LETTER
Power Supply Overlaid Communication with Common Clock Delivery for Cooperative Motion Control
Fumikazu MINAMIYAMA  Hidetsugu KOGA  Kentaro KOBAYASHI  Masaaki KATAYAMA  
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pp.2776-2779  LETTER
Subcarrier Mapping for Single-User SC-FDMA Relay Communications
Yu HEMMI  Koichi ADACHI  Tomoaki OHTSUKI  
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pp.2780-2786  LETTER
Iterations of FB-MSDSD and Turbo Codes over the Correlated Flat Fading Channel
Chien-Sheng CHEN  Ching-Chi LO  
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Special Section on Mathematical Systems Science and its Applications

pp.2787-2787  FOREWORD
FOREWORD
Toshimitsu USHIO  
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pp.2788-2793  INVITED PAPER
A Verification and Analysis Tool Set for Embedded System Design
Yuichi NAKAMURA  
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pp.2794-2801  PAPER
Checking On-the-Fly Universality and Inclusion Problems of Visibly Pushdown Automata
Nguyen VAN TANG  Hitoshi OHSAKI  
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pp.2802-2809  PAPER
Decentralized Supervisory Control of Timed Discrete Event Systems
Masashi NOMURA  Shigemasa TAKAI  
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pp.2810-2820  PAPER
Option-Based Monte Carlo Algorithm with Conditioned Updating to Learn Conflict-Free Task Allocation in Transport Applications
Alex VALDIVIELSO  Toshiyuki MIYAMOTO  
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pp.2821-2829  PAPER
Polynomial Time Verification of Behavioral Inheritance for Interworkflows Based on WfMC Protocol
Shingo YAMAGUCHI  Tomohiro HIRAKAWA  
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pp.2830-2831  LETTER
Simplified Relative Model to Measure Visual Fatigue in a Stereoscopy
Jae Gon KIM  Jun-Dong CHO  
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pp.2832-2835  LETTER
Verifying Structurally Weakly Persistent Net Is Co-NP Complete
Atsushi OHTA  Kohkichi TSUJI  
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Regular Section

pp.2836-2844  PAPER-Digital Signal Processing
Flicker Parameters Estimation in Old Film Sequences Containing Moving Objects
Xiaoyong ZHANG  Masahide ABE  Masayuki KAWAMATA  
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pp.2845-2852  PAPER-Nonlinear Problems
Self-Organizing Digital Spike Maps for Learning of Spike-Trains
Takashi OGAWA  Toshimichi SAITO  
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pp.2853-2865  PAPER-VLSI Design Technology and CAD
On Structural Analysis and Efficiency for Graph-Based Rewiring Techniques
Fu-Shing CHIM  Tak-Kei LAM  Yu-Liang WU  Hongbing FAN  
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pp.2866-2873  PAPER-Reliability, Maintainability and Safety Analysis
Adaptive Go-Back-N ARQ Protocol over Two Parallel Channels with Slow State Transition
Chun-Xiang CHEN  Kenichi NAGAOKA  Masaharu KOMATSU  
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pp.2874-2878  PAPER-Cryptography and Information Security
New Constructions of Binary Sequences with Good Autocorrelation Based on Interleaving Technique
Xiuwen MA  Qiaoyan WEN  Jie ZHANG  Xuan ZHANG  
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pp.2879-2885  PAPER-General Fundamentals and Boundaries
Approximate Bayesian Estimation of Varying Binomial Process
Kazuho WATANABE  Masato OKADA  
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pp.2886-2888  LETTER-Systems and Control
On the Monotonic Condition for Schur Stability of Real Polynomials
Younseok CHOO  Gin-Kyu CHOI  
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pp.2889-2893  LETTER-Cryptography and Information Security
Audio Watermarking Robust against Playback Speed Modification
Lili LI  Xiangzhong FANG  
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pp.2894-2899  LETTER-Coding Theory
Simultaneous Code/Error-Trellis Reduction for Convolutional Codes Using Shifted Code/Error-Subsequences
Masato TAJIMA  Koji OKINO  Takashi MIYAGOSHI  
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