IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences

Archive Index

Online ISSN : 1745-1337
Volume E93-A No.12  (Publication Date:2010/12/01)
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Regular Section (Invited Survey)

pp.2353-2353  FOREWORD
FOREWORD
Shoji SHINODA  
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pp.2354-2370  INVITED SURVEY PAPER
A Survey of the Origins and Evolution of the Microwave Circuit Devices in Japan from the 1920s up until 1945
Tosiro KOGA  
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Special Section on VLSI Design and CAD Algorithms

pp.2371-2371  FOREWORD
FOREWORD
Kazutoshi WAKABAYASHI  
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pp.2372-2379  PAPER-Physical Level Design
Redundant via Insertion: Removing Design Rule Conflicts and Balancing via Density
Song CHEN  Jianwei SHEN  Wei GUO  Mei-Fang CHIANG  Takeshi YOSHIMURA  
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pp.2380-2388  PAPER-Physical Level Design
CAFE Router: A Fast Connectivity Aware Multiple Nets Routing Algorithm for Routing Grid with Obstacles
Yukihide KOHIRA  Atsushi TAKAHASHI  
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pp.2389-2398  PAPER-Physical Level Design
Regularity-Oriented Analog Placement with Conditional Design Rules
Shigetoshi NAKATAKE  Masahiro KAWAKITA  Takao ITO  Masahiro KOJIMA  Michiko KOJIMA  Kenji IZUMI  Tadayuki HABASAKI  
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pp.2399-2408  PAPER-Device and Circuit Modeling and Analysis
Statistical Timing Analysis Considering Clock Jitter and Skew due to Power Supply Noise and Process Variation
Takashi ENAMI  Shinyu NINOMIYA  Ken-ichi SHINKAI  Shinya ABE  Masanori HASHIMOTO  
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pp.2409-2416  PAPER-Device and Circuit Modeling and Analysis
Linear Time Calculation of On-Chip Power Distribution Network Capacitance Considering State-Dependence
Shiho HAGIWARA  Koh YAMANAGA  Ryo TAKAHASHI  Kazuya MASU  Takashi SATO  
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pp.2417-2423  PAPER-Device and Circuit Modeling and Analysis
Measurement Circuits for Acquiring SET Pulse Width Distribution with Sub-FO1-Inverter-Delay Resolution
Ryo HARADA  Yukio MITSUYAMA  Masanori HASHIMOTO  Takao ONOYE  
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pp.2424-2432  PAPER-Device and Circuit Modeling and Analysis
Photomask Data Prioritization Based on VLSI Design Intent and Its Utilization for Mask Manufacturing
Kokoro KATO  Masakazu ENDO  Tadao INOUE  Shigetoshi NAKATAKE  Masaki YAMABE  Sunao ISHIHARA  
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pp.2433-2440  PAPER-Device and Circuit Modeling and Analysis
A Time Variant Analysis of Phase Noise in Differential Cross-Coupled LC Oscillators
Jinhua LIU  Guican CHEN  Hong ZHANG  
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pp.2441-2446  PAPER-Device and Circuit Modeling and Analysis
Accuracy Enhancement of Grid-Based SSTA by Coefficient Interpolation
Shinyu NINOMIYA  Masanori HASHIMOTO  
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pp.2447-2455  PAPER-Device and Circuit Modeling and Analysis
Gate Delay Estimation in STA under Dynamic Power Supply Noise
Takaaki OKUMURA  Fumihiro MINAMI  Kenji SHIMAZAKI  Kimihiko KUWADA  Masanori HASHIMOTO  
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pp.2456-2462  PAPER-Device and Circuit Modeling and Analysis
A Dynamic Offset Control Technique for Comparator Design in Scaled CMOS Technology
Xiaolei ZHU  Yanfei CHEN  Masaya KIBUNE  Yasumoto TOMITA  Takayuki HAMADA  Hirotaka TAMURA  Sanroku TSUKAMOTO  Tadahiro KURODA  
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pp.2463-2471  PAPER-Logic Synthesis, Test and Verification
Reduction of Area per Good Die for SoC Memory Built-In Self-Test
Masayuki ARAI  Tatsuro ENDO  Kazuhiko IWASAKI  Michinobu NAKAO  Iwao SUZUKI  
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pp.2472-2480  PAPER-Logic Synthesis, Test and Verification
Power Optimization of Sequential Circuits Using Switching Activity Based Clock Gating
Xin MAN  Takashi HORIYAMA  Shinji KIMURA  
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pp.2481-2489  PAPER-Logic Synthesis, Test and Verification
Scan-Based Side-Channel Attack against RSA Cryptosystems Using Scan Signatures
Ryuta NARA  Kei SATOH  Masao YANAGISAWA  Tatsuo OHTSUKI  Nozomu TOGAWA  
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pp.2490-2496  PAPER-Logic Synthesis, Test and Verification
An Error Diagnosis Technique Based on Clustering of Elements
Kosuke SHIOKI  Narumi OKADA  Kosuke WATANABE  Tetsuya HIROSE  Nobutaka KUROKI  Masahiro NUMA  
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pp.2497-2508  PAPER-Logic Synthesis, Test and Verification
A Design Methodology for a DPA-Resistant Circuit with RSL Techniques
Daisuke SUZUKI  Minoru SAEKI  Koichi SHIMIZU  Akashi SATOH  Tsutomu MATSUMOTO  
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pp.2509-2516  PAPER-High-Level Synthesis and System-Level Design
Automatic Communication Synthesis with Hardware Sharing for Multi-Processor SoC Design
Yuki ANDO  Seiya SHIBATA  Shinya HONDA  Hiroyuki TOMIYAMA  Hiroaki TAKADA  
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pp.2517-2523  PAPER-High-Level Synthesis and System-Level Design
Improved Dictionary-Based Code-Compression Schemes with XOR Reference for RISC/VLIW Architecture
Jui-Chun CHEN  Chang-Hong LIN  
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pp.2524-2532  PAPER-High-Level Synthesis and System-Level Design
Reliability Evaluation Environment for Exploring Design Space of Coarse-Grained Reconfigurable Architectures
Takashi IMAGAWA  Masayuki HIROMOTO  Hiroyuki OCHI  Takashi SATO  
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pp.2533-2541  PAPER-High-Level Synthesis and System-Level Design
A Multi-Performance Processor for Reducing the Energy Consumption of Real-Time Embedded Systems
Tohru ISHIHARA  
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pp.2542-2550  PAPER-High-Level Synthesis and System-Level Design
Variation-Aware Task and Communication Scheduling in MPSoCs for Power-Yield Maximization
Mahmoud MOMTAZPOUR  Maziar GOUDARZI  Esmaeil SANAEI  
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pp.2551-2559  PAPER-High-Level Synthesis and System-Level Design
Generic Permutation Network for QC-LDPC Decoder
Xiao PENG  Xiongxin ZHAO  Zhixiang CHEN  Fumiaki MAEHARA  Satoshi GOTO  
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pp.2560-2569  PAPER-High-Level Synthesis and System-Level Design
On Synthesizing a Reliable Multiprocessor for Embedded Systems
Makoto SUGIHARA  
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pp.2570-2580  PAPER-High-Level Synthesis and System-Level Design
Task Allocation with Algorithm Transformation for Reducing Data-Transfer Bottlenecks in Heterogeneous Multi-Core Processors: A Case Study of HOG Descriptor Computation
Hasitha Muthumala WAIDYASOORIYA  Daisuke OKUMURA  Masanori HARIYAMA  Michitaka KAMEYAMA  
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pp.2581-2589  PAPER-High-Level Synthesis and System-Level Design
Combined Use of Rising and Falling Edge Triggered Clocks for Peak Current Reduction in IP-Based SoC/NoC Designs
Tsung-Yi WU  Tzi-Wei KAO  How-Rern LIN  
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pp.2590-2599  PAPER-High-Level Synthesis and System-Level Design
HDLs Modeling Technique for Burst-Mode and Extended Burst-Mode Asynchronous Circuits
Jung-Lin YANG  Jau-Cheng WEI  Shin-Nung LU  
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pp.2600-2608  PAPER-Circuit Design
A 9-bit 100-MS/s 1.46-mW Tri-Level SAR ADC in 65 nm CMOS
Yanfei CHEN  Sanroku TSUKAMOTO  Tadahiro KURODA  
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pp.2609-2615  PAPER-Circuit Design
Low-Voltage Operational Active Inductor for LNA Circuit
Masaaki SODA  Ningyi WANG  Michio YOTSUYANAGI  
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pp.2616-2620  LETTER-Circuit Design
Subtraction Inversion for Delta Path's Hardware Simplification in MASH Delta-Sigma Modulator
Pao-Lung CHEN  
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pp.2621-2622  LETTER-Circuit Design
Low-Power High-Speed Data Serializer for Mobile TFT-LCD Driver ICs
Jae-Hyuck WOO  Jae-Goo LEE  Young-Hyun JUN  Bai-Sun KONG  
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Special Section on Wideband Systems

pp.2623-2623  FOREWORD
FOREWORD
Shinsuke HARA  
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pp.2624-2633  PAPER
Measurements and Modeling of Ultra-Wideband Propagation Losses around the Human Body Dependent on Room Volume
Hironobu YAMAMOTO  Masato KOIWAI  Takehiko KOBAYASHI  
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pp.2634-2645  PAPER
Doppler Spread Mitigation Using Harmonic Transform for Wireless OFDM Systems in Mobile Communications
Saiyan SAIYOD  Sakchai THIPCHAKSURAT  Ruttikorn VARAKULSIRIPUNTH  
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pp.2646-2653  PAPER
Channel Estimator Employing Narrowband Interference Detector of Wideband OFDM Receiver
Naohiko IWAKIRI  Takehiko KOBAYASHI  
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pp.2654-2662  PAPER
Performance Evaluation of Iterative LDPC-Coded MIMO OFDM System with Time Interleaving
Kazuhiko MITSUYAMA  Kohei KAMBARA  Takayuki NAKAGAWA  Tetsuomi IKEDA  Tomoaki OHTSUKI  
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pp.2663-2671  PAPER
Combined Trellis Precoding and Error Correcting Codes in Multi-User MIMO-OFDM Systems
Tsuguhide AOKI  Hideki OCHIAI  Ryuji KOHNO  
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pp.2672-2681  PAPER
Phase Rotation for Constructing Uniform Frequency Spectrum in IFDMA Communication
Takeo YAMASAKI  Osamu TAKYU  Koichi ADACHI  Yohtaro UMEDA  Masao NAKAGAWA  
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pp.2682-2690  PAPER
A Method of Cognizing Primary and Secondary Radio Signals
Satoshi TAKAHASHI  
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pp.2691-2695  LETTER
Time Domain Feedback Equalizer for Fast Fading Channel in OFDM with Scattered Pilot
Yutaro NAKAGAWA  Yukitoshi SANADA  
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pp.2696-2699  LETTER
Performance Bound for Turbo-Coded 2-D FSO/CDMA Systems over Atmospheric Turbulence Channels
Anh T. PHAM  Tu A. LUU  Ngoc T. DANG  
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pp.2700-2703  LETTER
On Communication and Interference Range of Multi-Gbps Millimeter-Wave WPAN System
Chin-Sean SUM  Zhou LAN  Junyi WANG  Hiroshi HARADA  Shuzo KATO  
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pp.2704-2707  LETTER
Prioritized Aggregation for Compressed Video Streaming on mmWave WPAN Systems
Zhou LAN  Chin Sean SUM  Junyi WANG  Hiroshi HARADA  Shuzo KATO  
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Special Section on Theory of Concurrent Systems and its Applications

pp.2708-2708  FOREWORD
FOREWORD
Satoshi TAOKA  
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pp.2709-2716  PAPER
Optimal Configuration for Multiversion Real-Time Systems Using Slack Based Schedulability
Sayuri TERADA  Toshimitsu USHIO  
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pp.2717-2729  PAPER
Delay Time Determination for the Timed Petri Net Model of a Signaling Pathway Based on Its Structural Information
Yoshimasa MIWA  Yuki MURAKAMI  Qi-Wei GE  Chen LI  Hiroshi MATSUNO  Satoru MIYANO  
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pp.2730-2739  PAPER
Parallel Degree of Well-Structured Workflow Nets
Nan QU  Shingo YAMAGUCHI  Qi-Wei GE  
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pp.2740-2743  LETTER
Rule-Based Ad-Hoc Workflow Modeling for Service Coordination: A Case Study of a Telecom Operational Support System
Jae-Yoon JUNG  Joonsoo BAE  
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Regular Section

pp.2744-2754  PAPER-Cryptography and Information Security
New Differential Cryptanalytic Results for Reduced-Round CAST-128
Meiqin WANG  Xiaoyun WANG  Kam Pui CHOW  Lucas Chi Kwong HUI  
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pp.2755-2757  LETTER-Circuit Theory
A Low Complexity Dual-Mode Pulse-Triggered Flip-Flop Design Based on Unified AND/XNOR Logic
Jin-Fa LIN  Yin-Tshung HWANG  Ming-Hwa SHEU  
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pp.2758-2761  LETTER-Information Theory
On (1) Error Correctable Integer Codes
Hristo KOSTADINOV  Hiroyoshi MORITA  Nikolai MANEV  
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