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IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences

Archive Index

Online ISSN : 1745-1337

Volume E92-A No.12 (Publication Date:2009/12/01)

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Special Section on VLSI Design and CAD Algorithms

pp.2961-2961 FOREWORD FOREWORD Shinji KIMURA
	Summary \| Full Text:PDF (54KB)

pp.2962-2970 PAPER-Physical Level Desing Practical Redundant-Via Insertion Method Considering Manufacturing Variability and Reliability Yuji TAKASHIMA Kazuyuki OOYA Atsushi KUROKAWA
	Summary \| Full Text:PDF (489KB)

pp.2971-2978 PAPER-Physical Level Desing A Fast Longer Path Algorithm for Routing Grid with Obstacles Using Biconnectivity Based Length Upper Bound Yukihide KOHIRA Suguru SUEHIRO Atsushi TAKAHASHI
	Summary \| Full Text:PDF (750.2KB)

pp.2979-2989 PAPER-Physical Level Desing Thermal-Aware Incremental Floorplanning for 3D ICs Based on MILP Formulation Yuchun MA Xin LI Yu WANG Xianlong HONG
	Summary \| Full Text:PDF (535.8KB)

pp.2990-2997 PAPER-Physical Level Desing Voltage and Level-Shifter Assignment Driven Floorplanning Bei YU Sheqin DONG Song CHEN Satoshi GOTO
	Summary \| Full Text:PDF (512.1KB)

pp.2998-3006 PAPER-Physical Level Desing MILP-Based Efficient Routing Method with Restricted Route Structure for 2-Layer Ball Grid Array Packages Yoichi TOMIOKA Yoshiaki KURATA Yukihide KOHIRA Atsushi TAKAHASHI
	Summary \| Full Text:PDF (479.5KB)

pp.3007-3015 PAPER-Device and Circuit Modeling and Analysis Intra-Die Spatial Correlation Extraction with Maximum Likelihood Estimation Method for Multiple Test Chips Qiang FU Wai-Shing LUK Jun TAO Xuan ZENG Wei CAI
	Summary \| Full Text:PDF (423KB)

pp.3016-3023 PAPER-Device and Circuit Modeling and Analysis An Approach for Reducing Leakage Current Variation due to Manufacturing Variability Tsuyoshi SAKATA Takaaki OKUMURA Atsushi KUROKAWA Hidenari NAKASHIMA Hiroo MASUDA Takashi SATO Masanori HASHIMOTO Koutaro HACHIYA Katsuhiro FURUKAWA Masakazu TANAKA Hiroshi TAKAFUJI Toshiki KANAMOTO
	Summary \| Full Text:PDF (1.1MB)

pp.3024-3034 PAPER-Device and Circuit Modeling and Analysis A Modified Nested Sparse Grid Based Adaptive Stochastic Collocation Method for Statistical Static Timing Analysis Xu LUO Fan YANG Xuan ZENG Jun TAO Hengliang ZHU Wei CAI
	Summary \| Full Text:PDF (434.2KB)

pp.3035-3043 PAPER-Device and Circuit Modeling and Analysis Find the 'Best' Solution from Multiple Analog Topologies via Pareto-Optimality Yu LIU Masato YOSHIOKA Katsumi HOMMA Toshiyuki SHIBUYA
	Summary \| Full Text:PDF (990.7KB)

pp.3044-3051 PAPER-Device and Circuit Modeling and Analysis Design of Voltage-Mode MAX-MIN Circuits with Low Area and Low Power Consumption Mohammad SOLEIMANI Abdollah KHOEI Khayrollah HADIDI Vahid Fagih DINAVARI
	Summary \| Full Text:PDF (881.9KB)

pp.3052-3060 PAPER-Device and Circuit Modeling and Analysis Fast Shape Optimization of Metalization Patterns for Power-MOSFET Based Driver Bo YANG Shigetoshi NAKATAKE
	Summary \| Full Text:PDF (365.4KB)

pp.3061-3069 PAPER-Device and Circuit Modeling and Analysis Fast Analysis of On-Chip Power Grid Circuits by Extended Truncated Balanced Realization Method Duo LI Sheldon X.-D. TAN
	Summary \| Full Text:PDF (884.7KB)

pp.3070-3078 PAPER-Device and Circuit Modeling and Analysis Statistical Gate Delay Model for Multiple Input Switching Takayuki FUKUOKA Akira TSUCHIYA Hidetoshi ONODERA
	Summary \| Full Text:PDF (441.4KB)

pp.3079-3081 LETTER-Device and Circuit Modeling and Analysis Low-Voltage Process-Compensated VCO with On-Chip Process Monitoring and Body-Biasing Circuit Techniques Ken UENO Tetsuya HIROSE Tetsuya ASAI Yoshihito AMEMIYA
	Summary \| Full Text:PDF (314KB)

pp.3082-3085 LETTER-Device and Circuit Modeling and Analysis Accurate Systematic Hot-Spot Scoring Method and Score-Based Fixing Guidance Generation Yonghee PARK Junghoe CHOI Jisuk HONG Sanghoon LEE Moonhyun YOO Jundong CHO
	Summary \| Full Text:PDF (587.4KB)

pp.3086-3093 PAPER-Logic Synthesis, Test and Verfication Constrained Stimulus Generation with Self-Adjusting Using Tabu Search with Memory Yanni ZHAO Jinian BIAN Shujun DENG Zhiqiu KONG Kang ZHAO
	Summary \| Full Text:PDF (300.6KB)

pp.3094-3102 PAPER-Logic Synthesis, Test and Verfication Trade-Off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction Hiroshi FUKETA Masanori HASHIMOTO Yukio MITSUYAMA Takao ONOYE
	Summary \| Full Text:PDF (611KB)

pp.3103-3110 PAPER-Logic Synthesis, Test and Verfication Incremental Buffer Insertion and Module Resizing Algorithm Using Geometric Programming Qing DONG Bo YANG Jing LI Shigetoshi NAKATAKE
	Summary \| Full Text:PDF (335.1KB)

pp.3111-3118 PAPER-Logic Synthesis, Test and Verfication Optimizing Controlling-Value-Based Power Gating with Gate Count and Switching Activity Lei CHEN Shinji KIMURA
	Summary \| Full Text:PDF (561.5KB)

pp.3119-3127 PAPER-Logic Synthesis, Test and Verfication X-Handling for Current X-Tolerant Compactors with More Unknowns and Maximal Compaction Youhua SHI Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI
	Summary \| Full Text:PDF (850.7KB)

pp.3128-3135 PAPER-Logic Synthesis, Test and Verfication Addressing Defect Coverage through Generating Test Vectors for Transistor Defects Yoshinobu HIGAMI Kewal K. SALUJA Hiroshi TAKAHASHI Shin-ya KOBAYASHI Yuzo TAKAMATSU
	Summary \| Full Text:PDF (298.7KB)

pp.3136-3142 PAPER-Logic Synthesis, Test and Verfication An Error Diagnosis Technique Based on Location Sets to Rectify Subcircuits Kosuke SHIOKI Narumi OKADA Toshiro ISHIHARA Tetsuya HIROSE Nobutaka KUROKI Masahiro NUMA
	Summary \| Full Text:PDF (925.4KB)

pp.3143-3150 PAPER-High-Level Synthesis and System-Level Design Communication Synthesis for Interconnect Minimization in Multicycle Communication Architecture Ya-Shih HUANG Yu-Ju HONG Juinn-Dar HUANG
	Summary \| Full Text:PDF (1.2MB)

pp.3151-3159 PAPER-High-Level Synthesis and System-Level Design Peak Temperature Reduction by Physical Information Driven Behavioral Synthesis with Resource Usage Allocation Junbo YU Qiang ZHOU Gang QU Jinian BIAN
	Summary \| Full Text:PDF (1MB)

pp.3160-3168 PAPER-High-Level Synthesis and System-Level Design Energy-Aware Memory Allocation Framework for Embedded Data-Intensive Signal Processing Applications Florin BALASA Ilie I. LUICAN Hongwei ZHU Doru V. NASUI
	Summary \| Full Text:PDF (400.3KB)

pp.3169-3179 PAPER-High-Level Synthesis and System-Level Design Floorplan-Aware High-Level Synthesis for Generalized Distributed-Register Architectures Akira OHCHI Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI
	Summary \| Full Text:PDF (824.3KB)

pp.3180-3181 LETTER-High-Level Synthesis and System-Level Design Low-Power Embedded Processor Design Using Branch Direction Gi-Ho PARK Jung-Wook PARK Gunok JUNG Shin-Dug KIM
	Summary \| Full Text:PDF (343.4KB)

pp.3182-3192 PAPER-Embedded, Real-Time and Reconfigurable Systems Rapid Design Space Exploration of a Reconfigurable Instruction-Set Processor Farhad MEHDIPOUR Hamid NOORI Koji INOUE Kazuaki MURAKAMI
	Summary \| Full Text:PDF (1005.6KB)

pp.3193-3202 PAPER-Embedded, Real-Time and Reconfigurable Systems A System-Level Model of Design Space Exploration for a Tile-Based 3D Graphics SoC Refinement Liang-Bi CHEN Chi-Tsai YEH Hung-Yu CHEN Ing-Jer HUANG
	Summary \| Full Text:PDF (1MB)

pp.3203-3210 PAPER-Embedded, Real-Time and Reconfigurable Systems A 48 Cycles/MB H.264/AVC Deblocking Filter Architecture for Ultra High Definition Applications Dajiang ZHOU Jinjia ZHOU Jiayi ZHU Satoshi GOTO
	Summary \| Full Text:PDF (2.1MB)

pp.3211-3220 PAPER-Embedded, Real-Time and Reconfigurable Systems Worst-Case Flit and Packet Delay Bounds in Wormhole Networks on Chip Yue QIAN Zhonghai LU Wenhua DOU
	Summary \| Full Text:PDF (1MB)

pp.3221-3228 PAPER-Embedded, Real-Time and Reconfigurable Systems Low Cost Design of an Advanced Encryption Standard (AES) Processor Using a New Common-Subexpression-Elimination Algorithm Ming-Chih CHEN Shen-Fu HSIAO
	Summary \| Full Text:PDF (1007.8KB)

pp.3229-3237 PAPER-Embedded, Real-Time and Reconfigurable Systems A Scan-Based Attack Based on Discriminators for AES Cryptosystems Ryuta NARA Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI
	Summary \| Full Text:PDF (1.2MB)

pp.3238-3247 PAPER-Embedded, Real-Time and Reconfigurable Systems A Two-Level Cache Design Space Exploration System for Embedded Applications Nobuaki TOJO Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI
	Summary \| Full Text:PDF (521KB)

pp.3248-3257 PAPER-Embedded, Real-Time and Reconfigurable Systems Entropy Decoding Processor for Modern Multimedia Applications Sumek WISAYATAKSIN Dongju LI Tsuyoshi ISSHIKI Hiroaki KUNIEDA
	Summary \| Full Text:PDF (787KB)

pp.3258-3267 PAPER-Embedded, Real-Time and Reconfigurable Systems Heuristic Instruction Scheduling Algorithm Using Available Distance for Partial Forwarding Processor Takuji HIEDA Hiroaki TANAKA Keishi SAKANUSHI Yoshinori TAKEUCHI Masaharu IMAI
	Summary \| Full Text:PDF (560KB)

pp.3268-3275 PAPER-Embedded, Real-Time and Reconfigurable Systems Efficient Cut Enumeration Heuristics for Depth-Optimum Technology Mapping for LUT-Based FPGAs Taiga TAKATA Yusuke MATSUNAGA
	Summary \| Full Text:PDF (338.5KB)

Special Section on Image Media Quality

pp.3276-3276 FOREWORD FOREWORD Mitsuho YAMADA
	Summary \| Full Text:PDF (58KB)

pp.3277-3283 PAPER-INVITED Two Principles of High-Level Human Visual Processing Potentially Useful for Image and Video Quality Assessment Shin'ya NISHIDA
	Summary \| Full Text:PDF (419.8KB)

pp.3284-3290 PAPER-Evaluation Video-Quality Estimation Based on Reduced-Reference Model Employing Activity-Difference Toru YAMADA Yoshihiro MIYAMOTO Yuzo SENDA Masahiro SERIZAWA
	Summary \| Full Text:PDF (418.1KB)

pp.3291-3296 PAPER-Evaluation Estimation of Mosquito Noise Level from Decoded Picture Kenji SUGIYAMA Naoya SAGARA Yohei KASHIMURA
	Summary \| Full Text:PDF (1.2MB)

pp.3297-3306 PAPER-Evaluation Non-intrusive Packet-Layer Model for Monitoring Video Quality of IPTV Services Kazuhisa YAMAGISHI Takanori HAYASHI
	Summary \| Full Text:PDF (388.9KB)

pp.3307-3312 PAPER-Evaluation Objective Evaluation of Components of Colour Distortions due to Image Compression Amal PUNCHIHEWA Jonathan ARMSTRONG Seiichiro HANGAI Takayuki HAMAMOTO
	Summary \| Full Text:PDF (653.7KB)

pp.3313-3320 PAPER-Imaging Detection and Classification of Invariant Blurs Rachel Mabanag CHONG Toshihisa TANAKA
	Summary \| Full Text:PDF (543.7KB)

pp.3321-3327 PAPER-Imaging The Effects of Sensor Spectral Sensitivity, Pixel Pitch, Photon Shot Noise, and Dark Noise on Perceived Image Quality Hideyasu KUNIBA Roy S. BERNS
	Summary \| Full Text:PDF (654.8KB)

pp.3328-3335 PAPER-Printing A Simple Method to Measure MTF of Paper and Its Application for Dot Gain Analysis Masayuki UKISHIMA Hitomi KANEKO Toshiya NAKAGUCHI Norimichi TSUMURA Markku HAUTA-KASARI Jussi PARKKINEN Yoichi MIYAKE
	Summary \| Full Text:PDF (955KB)

pp.3336-3343 PAPER-Processing Face Alignment Based on Statistical Models Using SIFT Descriptors Zisheng LI Jun-ichi IMAI Masahide KANEKO
	Summary \| Full Text:PDF (868.2KB)

pp.3344-3354 PAPER-Processing Image Restoration Based on Adaptive Directional Regularization Osama AHMED OMER Toshihisa TANAKA
	Summary \| Full Text:PDF (504KB)

pp.3355-3360 PAPER-Coding An Improved Method to CABAC in the H.264/AVC Video Compression Standard LeThanh HA Chun-Su PARK Seung-Won JUNG Sung-Jea KO
	Summary \| Full Text:PDF (277.3KB)

pp.3361-3368 PAPER-Coding Macroblock and Motion Feature Analysis to H.264/AVC Fast Inter Mode Decision Yiqing HUANG Qin LIU Shuijiong WU Zhewen ZHENG Takeshi IKENAGA
	Summary \| Full Text:PDF (922.5KB)

pp.3369-3371 LETTER-Coding Improved Vector Quantization Based Block Truncation Coding Using Template Matching and Lloyd Quantization Seung-Won JUNG Yeo-Jin YOON Hyeong-Min NAM Sung-Jea KO
	Summary \| Full Text:PDF (186.7KB)

pp.3372-3375 LETTER-Color Adaptive Ambient Illumination Based on Color Harmony Model Ayano KIKUCHI Keita HIRAI Toshiya NAKAGUCHI Norimichi TSUMURA Yoichi MIYAKE
	Summary \| Full Text:PDF (222.3KB)

Regular Section

pp.3376-3380 PAPER-Systems and Control Boundary Implications for Stability Analysis of a Class of Uncertain Linear Time-Delay Systems by the Lambert W Function Hiroshi SHINOZAKI Takehiro MORI
	Summary \| Full Text:PDF (190.9KB)

pp.3381-3389 PAPER-VLSI Design Technology and CAD Ultra Low Power Delay Element with Post-Chip Adjustable Ability Jung-Lin YANG Chih-Wei CHAO
	Summary \| Full Text:PDF (930.4KB)

pp.3390-3393 LETTER-Systems and Control Deadbeat Control for Linear Systems with Input Constraints Dane BAANG Dongkyoung CHWA
	Summary \| Full Text:PDF (149.9KB)

pp.3394-3397 LETTER-Nonlinear Problems Performance Analysis of Complex CDMA Using Complex Chaotic Spreading Sequence with Constant Power Ryo TAKAHASHI Ken UMENO
	Summary \| Full Text:PDF (92.1KB)

pp.3398-3400 LETTER-Algorithms and Data Structures A Simple Canonical Code for Fullerene Graphs Naoki SHIMOTSUMA Shin-ichi NAKANO
	Summary \| Full Text:PDF (245.2KB)

pp.3401-3403 LETTER-Cryptography and Information Security Hash Functions and Information Theoretic Security Nasour BAGHERI Lars R. KNUDSEN Majid NADERI Sφren S. THOMSEN
	Summary \| Full Text:PDF (71.5KB)

pp.3404-3406 LETTER-Spread Spectrum Technologies and Applications Constructions of Factorizable Multilevel Hadamard Matrices Shinya MATSUFUJI Pingzhi FAN
	Summary \| Full Text:PDF (65.9KB)

pp.3407-3411 LETTER-Image Fast Mode Decision Using Global Disparity Vector for Multiview Video Coding Dong-Hoon HAN Yung-Ki LEE Yung-Lyul LEE
	Summary \| Full Text:PDF (803KB)