IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences

Archive Index

Online ISSN : 1745-1337
Volume E92-A No.12  (Publication Date:2009/12/01)
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Special Section on VLSI Design and CAD Algorithms

pp.2961-2961  FOREWORD
FOREWORD
Shinji KIMURA  
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pp.2962-2970  PAPER-Physical Level Desing
Practical Redundant-Via Insertion Method Considering Manufacturing Variability and Reliability
Yuji TAKASHIMA  Kazuyuki OOYA  Atsushi KUROKAWA  
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pp.2971-2978  PAPER-Physical Level Desing
A Fast Longer Path Algorithm for Routing Grid with Obstacles Using Biconnectivity Based Length Upper Bound
Yukihide KOHIRA  Suguru SUEHIRO  Atsushi TAKAHASHI  
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pp.2979-2989  PAPER-Physical Level Desing
Thermal-Aware Incremental Floorplanning for 3D ICs Based on MILP Formulation
Yuchun MA  Xin LI  Yu WANG  Xianlong HONG  
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pp.2990-2997  PAPER-Physical Level Desing
Voltage and Level-Shifter Assignment Driven Floorplanning
Bei YU  Sheqin DONG  Song CHEN  Satoshi GOTO  
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pp.2998-3006  PAPER-Physical Level Desing
MILP-Based Efficient Routing Method with Restricted Route Structure for 2-Layer Ball Grid Array Packages
Yoichi TOMIOKA  Yoshiaki KURATA  Yukihide KOHIRA  Atsushi TAKAHASHI  
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pp.3007-3015  PAPER-Device and Circuit Modeling and Analysis
Intra-Die Spatial Correlation Extraction with Maximum Likelihood Estimation Method for Multiple Test Chips
Qiang FU  Wai-Shing LUK  Jun TAO  Xuan ZENG  Wei CAI  
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pp.3016-3023  PAPER-Device and Circuit Modeling and Analysis
An Approach for Reducing Leakage Current Variation due to Manufacturing Variability
Tsuyoshi SAKATA  Takaaki OKUMURA  Atsushi KUROKAWA  Hidenari NAKASHIMA  Hiroo MASUDA  Takashi SATO  Masanori HASHIMOTO  Koutaro HACHIYA  Katsuhiro FURUKAWA  Masakazu TANAKA  Hiroshi TAKAFUJI  Toshiki KANAMOTO  
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pp.3024-3034  PAPER-Device and Circuit Modeling and Analysis
A Modified Nested Sparse Grid Based Adaptive Stochastic Collocation Method for Statistical Static Timing Analysis
Xu LUO  Fan YANG  Xuan ZENG  Jun TAO  Hengliang ZHU  Wei CAI  
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pp.3035-3043  PAPER-Device and Circuit Modeling and Analysis
Find the 'Best' Solution from Multiple Analog Topologies via Pareto-Optimality
Yu LIU  Masato YOSHIOKA  Katsumi HOMMA  Toshiyuki SHIBUYA  
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pp.3044-3051  PAPER-Device and Circuit Modeling and Analysis
Design of Voltage-Mode MAX-MIN Circuits with Low Area and Low Power Consumption
Mohammad SOLEIMANI  Abdollah KHOEI  Khayrollah HADIDI  Vahid Fagih DINAVARI  
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pp.3052-3060  PAPER-Device and Circuit Modeling and Analysis
Fast Shape Optimization of Metalization Patterns for Power-MOSFET Based Driver
Bo YANG  Shigetoshi NAKATAKE  
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pp.3061-3069  PAPER-Device and Circuit Modeling and Analysis
Fast Analysis of On-Chip Power Grid Circuits by Extended Truncated Balanced Realization Method
Duo LI  Sheldon X.-D. TAN  
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pp.3070-3078  PAPER-Device and Circuit Modeling and Analysis
Statistical Gate Delay Model for Multiple Input Switching
Takayuki FUKUOKA  Akira TSUCHIYA  Hidetoshi ONODERA  
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pp.3079-3081  LETTER-Device and Circuit Modeling and Analysis
Low-Voltage Process-Compensated VCO with On-Chip Process Monitoring and Body-Biasing Circuit Techniques
Ken UENO  Tetsuya HIROSE  Tetsuya ASAI  Yoshihito AMEMIYA  
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pp.3082-3085  LETTER-Device and Circuit Modeling and Analysis
Accurate Systematic Hot-Spot Scoring Method and Score-Based Fixing Guidance Generation
Yonghee PARK  Junghoe CHOI  Jisuk HONG  Sanghoon LEE  Moonhyun YOO  Jundong CHO  
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pp.3086-3093  PAPER-Logic Synthesis, Test and Verfication
Constrained Stimulus Generation with Self-Adjusting Using Tabu Search with Memory
Yanni ZHAO  Jinian BIAN  Shujun DENG  Zhiqiu KONG  Kang ZHAO  
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pp.3094-3102  PAPER-Logic Synthesis, Test and Verfication
Trade-Off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction
Hiroshi FUKETA  Masanori HASHIMOTO  Yukio MITSUYAMA  Takao ONOYE  
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pp.3103-3110  PAPER-Logic Synthesis, Test and Verfication
Incremental Buffer Insertion and Module Resizing Algorithm Using Geometric Programming
Qing DONG  Bo YANG  Jing LI  Shigetoshi NAKATAKE  
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pp.3111-3118  PAPER-Logic Synthesis, Test and Verfication
Optimizing Controlling-Value-Based Power Gating with Gate Count and Switching Activity
Lei CHEN  Shinji KIMURA  
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pp.3119-3127  PAPER-Logic Synthesis, Test and Verfication
X-Handling for Current X-Tolerant Compactors with More Unknowns and Maximal Compaction
Youhua SHI  Nozomu TOGAWA  Masao YANAGISAWA  Tatsuo OHTSUKI  
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pp.3128-3135  PAPER-Logic Synthesis, Test and Verfication
Addressing Defect Coverage through Generating Test Vectors for Transistor Defects
Yoshinobu HIGAMI  Kewal K. SALUJA  Hiroshi TAKAHASHI  Shin-ya KOBAYASHI  Yuzo TAKAMATSU  
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pp.3136-3142  PAPER-Logic Synthesis, Test and Verfication
An Error Diagnosis Technique Based on Location Sets to Rectify Subcircuits
Kosuke SHIOKI  Narumi OKADA  Toshiro ISHIHARA  Tetsuya HIROSE  Nobutaka KUROKI  Masahiro NUMA  
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pp.3143-3150  PAPER-High-Level Synthesis and System-Level Design
Communication Synthesis for Interconnect Minimization in Multicycle Communication Architecture
Ya-Shih HUANG  Yu-Ju HONG  Juinn-Dar HUANG  
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pp.3151-3159  PAPER-High-Level Synthesis and System-Level Design
Peak Temperature Reduction by Physical Information Driven Behavioral Synthesis with Resource Usage Allocation
Junbo YU  Qiang ZHOU  Gang QU  Jinian BIAN  
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pp.3160-3168  PAPER-High-Level Synthesis and System-Level Design
Energy-Aware Memory Allocation Framework for Embedded Data-Intensive Signal Processing Applications
Florin BALASA  Ilie I. LUICAN  Hongwei ZHU  Doru V. NASUI  
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pp.3169-3179  PAPER-High-Level Synthesis and System-Level Design
Floorplan-Aware High-Level Synthesis for Generalized Distributed-Register Architectures
Akira OHCHI  Nozomu TOGAWA  Masao YANAGISAWA  Tatsuo OHTSUKI  
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pp.3180-3181  LETTER-High-Level Synthesis and System-Level Design
Low-Power Embedded Processor Design Using Branch Direction
Gi-Ho PARK  Jung-Wook PARK  Gunok JUNG  Shin-Dug KIM  
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pp.3182-3192  PAPER-Embedded, Real-Time and Reconfigurable Systems
Rapid Design Space Exploration of a Reconfigurable Instruction-Set Processor
Farhad MEHDIPOUR  Hamid NOORI  Koji INOUE  Kazuaki MURAKAMI  
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pp.3193-3202  PAPER-Embedded, Real-Time and Reconfigurable Systems
A System-Level Model of Design Space Exploration for a Tile-Based 3D Graphics SoC Refinement
Liang-Bi CHEN  Chi-Tsai YEH  Hung-Yu CHEN  Ing-Jer HUANG  
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pp.3203-3210  PAPER-Embedded, Real-Time and Reconfigurable Systems
A 48 Cycles/MB H.264/AVC Deblocking Filter Architecture for Ultra High Definition Applications
Dajiang ZHOU  Jinjia ZHOU  Jiayi ZHU  Satoshi GOTO  
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pp.3211-3220  PAPER-Embedded, Real-Time and Reconfigurable Systems
Worst-Case Flit and Packet Delay Bounds in Wormhole Networks on Chip
Yue QIAN  Zhonghai LU  Wenhua DOU  
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pp.3221-3228  PAPER-Embedded, Real-Time and Reconfigurable Systems
Low Cost Design of an Advanced Encryption Standard (AES) Processor Using a New Common-Subexpression-Elimination Algorithm
Ming-Chih CHEN  Shen-Fu HSIAO  
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pp.3229-3237  PAPER-Embedded, Real-Time and Reconfigurable Systems
A Scan-Based Attack Based on Discriminators for AES Cryptosystems
Ryuta NARA  Nozomu TOGAWA  Masao YANAGISAWA  Tatsuo OHTSUKI  
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pp.3238-3247  PAPER-Embedded, Real-Time and Reconfigurable Systems
A Two-Level Cache Design Space Exploration System for Embedded Applications
Nobuaki TOJO  Nozomu TOGAWA  Masao YANAGISAWA  Tatsuo OHTSUKI  
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pp.3248-3257  PAPER-Embedded, Real-Time and Reconfigurable Systems
Entropy Decoding Processor for Modern Multimedia Applications
Sumek WISAYATAKSIN  Dongju LI  Tsuyoshi ISSHIKI  Hiroaki KUNIEDA  
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pp.3258-3267  PAPER-Embedded, Real-Time and Reconfigurable Systems
Heuristic Instruction Scheduling Algorithm Using Available Distance for Partial Forwarding Processor
Takuji HIEDA  Hiroaki TANAKA  Keishi SAKANUSHI  Yoshinori TAKEUCHI  Masaharu IMAI  
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pp.3268-3275  PAPER-Embedded, Real-Time and Reconfigurable Systems
Efficient Cut Enumeration Heuristics for Depth-Optimum Technology Mapping for LUT-Based FPGAs
Taiga TAKATA  Yusuke MATSUNAGA  
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Special Section on Image Media Quality

pp.3276-3276  FOREWORD
FOREWORD
Mitsuho YAMADA  
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pp.3277-3283  INVITED PAPER
Two Principles of High-Level Human Visual Processing Potentially Useful for Image and Video Quality Assessment
Shin'ya NISHIDA  
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pp.3284-3290  PAPER-Evaluation
Video-Quality Estimation Based on Reduced-Reference Model Employing Activity-Difference
Toru YAMADA  Yoshihiro MIYAMOTO  Yuzo SENDA  Masahiro SERIZAWA  
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pp.3291-3296  PAPER-Evaluation
Estimation of Mosquito Noise Level from Decoded Picture
Kenji SUGIYAMA  Naoya SAGARA  Yohei KASHIMURA  
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pp.3297-3306  PAPER-Evaluation
Non-intrusive Packet-Layer Model for Monitoring Video Quality of IPTV Services
Kazuhisa YAMAGISHI  Takanori HAYASHI  
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pp.3307-3312  PAPER-Evaluation
Objective Evaluation of Components of Colour Distortions due to Image Compression
Amal PUNCHIHEWA  Jonathan ARMSTRONG  Seiichiro HANGAI  Takayuki HAMAMOTO  
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pp.3313-3320  PAPER-Imaging
Detection and Classification of Invariant Blurs
Rachel Mabanag CHONG  Toshihisa TANAKA  
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pp.3321-3327  PAPER-Imaging
The Effects of Sensor Spectral Sensitivity, Pixel Pitch, Photon Shot Noise, and Dark Noise on Perceived Image Quality
Hideyasu KUNIBA  Roy S. BERNS  
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pp.3328-3335  PAPER-Printing
A Simple Method to Measure MTF of Paper and Its Application for Dot Gain Analysis
Masayuki UKISHIMA  Hitomi KANEKO  Toshiya NAKAGUCHI  Norimichi TSUMURA  Markku HAUTA-KASARI  Jussi PARKKINEN  Yoichi MIYAKE  
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pp.3336-3343  PAPER-Processing
Face Alignment Based on Statistical Models Using SIFT Descriptors
Zisheng LI  Jun-ichi IMAI  Masahide KANEKO  
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pp.3344-3354  PAPER-Processing
Image Restoration Based on Adaptive Directional Regularization
Osama AHMED OMER  Toshihisa TANAKA  
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pp.3355-3360  PAPER-Coding
An Improved Method to CABAC in the H.264/AVC Video Compression Standard
LeThanh HA  Chun-Su PARK  Seung-Won JUNG  Sung-Jea KO  
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pp.3361-3368  PAPER-Coding
Macroblock and Motion Feature Analysis to H.264/AVC Fast Inter Mode Decision
Yiqing HUANG  Qin LIU  Shuijiong WU  Zhewen ZHENG  Takeshi IKENAGA  
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pp.3369-3371  LETTER-Coding
Improved Vector Quantization Based Block Truncation Coding Using Template Matching and Lloyd Quantization
Seung-Won JUNG  Yeo-Jin YOON  Hyeong-Min NAM  Sung-Jea KO  
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pp.3372-3375  LETTER-Color
Adaptive Ambient Illumination Based on Color Harmony Model
Ayano KIKUCHI  Keita HIRAI  Toshiya NAKAGUCHI  Norimichi TSUMURA  Yoichi MIYAKE  
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Regular Section

pp.3376-3380  PAPER-Systems and Control
Boundary Implications for Stability Analysis of a Class of Uncertain Linear Time-Delay Systems by the Lambert W Function
Hiroshi SHINOZAKI  Takehiro MORI  
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pp.3381-3389  PAPER-VLSI Design Technology and CAD
Ultra Low Power Delay Element with Post-Chip Adjustable Ability
Jung-Lin YANG  Chih-Wei CHAO  
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pp.3390-3393  LETTER-Systems and Control
Deadbeat Control for Linear Systems with Input Constraints
Dane BAANG  Dongkyoung CHWA  
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pp.3394-3397  LETTER-Nonlinear Problems
Performance Analysis of Complex CDMA Using Complex Chaotic Spreading Sequence with Constant Power
Ryo TAKAHASHI  Ken UMENO  
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pp.3398-3400  LETTER-Algorithms and Data Structures
A Simple Canonical Code for Fullerene Graphs
Naoki SHIMOTSUMA  Shin-ichi NAKANO  
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pp.3401-3403  LETTER-Cryptography and Information Security
Hash Functions and Information Theoretic Security
Nasour BAGHERI  Lars R. KNUDSEN  Majid NADERI  Sφren S. THOMSEN  
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pp.3404-3406  LETTER-Spread Spectrum Technologies and Applications
Constructions of Factorizable Multilevel Hadamard Matrices
Shinya MATSUFUJI  Pingzhi FAN  
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pp.3407-3411  LETTER-Image
Fast Mode Decision Using Global Disparity Vector for Multiview Video Coding
Dong-Hoon HAN  Yung-Ki LEE  Yung-Lyul LEE  
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