IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences

Archive Index

Online ISSN : 1745-1337
Volume E90-A No.12  (Publication Date:2007/12/01)
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Special Section on VLSI Design and CAD Algorithms

pp.2649-2650  FOREWORD
FOREWORD
Yusuke MATSUNAGA  
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pp.2651-2660  PAPER-Physical Design
Chip-Level Substrate Coupling Analysis with Reference Structures for Verification
Daisuke KOSAKA  Makoto NAGATA  Yoshitaka MURASAKA  Atsushi IWATA  
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pp.2661-2668  PAPER-Physical Design
Timing Analysis Considering Spatial Power/Ground Level Variation
Masanori HASHIMOTO  Junji YAMAGUCHI  Hidetoshi ONODERA  
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pp.2669-2681  PAPER-Physical Design
Closed-Form Expressions for Crosstalk Noise and Worst-Case Delay on Capacitively Coupled Distributed RC Lines
Hiroshi KAWAGUCHI  Danardono Dwi ANTONO  Takayasu SAKURAI  
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pp.2682-2690  PAPER-Physical Design
Manufacturability-Aware Design of Standard Cells
Hirokazu MUTA  Hidetoshi ONODERA  
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pp.2691-2694  LETTER-Memory Design and Test
Look-Ahead Dynamic Threshold Voltage Control Scheme for Improving Write Margin of SOI-7T-SRAM
Masaaki IIJIMA  Kayoko SETO  Masahiro NUMA  Akira TADA  Takashi IPPOSHI  
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pp.2695-2702  PAPER-Memory Design and Test
Area Comparison between 6T and 8T SRAM Cells in Dual-Vdd Scheme and DVS Scheme
Yasuhiro MORITA  Hidehiro FUJIWARA  Hiroki NOGUCHI  Yusuke IGUCHI  Koji NII  Hiroshi KAWAGUCHI  Masahiko YOSHIMOTO  
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pp.2703-2711  PAPER-Memory Design and Test
An Efficient Diagnosis Scheme for RAMs with Simple Functional Faults
Jin-Fu LI  Chao-Da HUANG  
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pp.2712-2717  LETTER-Circuit Synthesis
Transistor Sizing of LCD Driver Circuit for Technology Migration
Masanori HASHIMOTO  Takahito IJICHI  Shingo TAKAHASHI  Shuji TSUKIYAMA  Isao SHIRAKAWA  
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pp.2718-2726  PAPER-Circuit Synthesis
A Fast Probability-Based Algorithm for Leakage Current Reduction Considering Controller Cost
Tsung-Yi WU  Jr-Luen TZENG  
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pp.2727-2735  PAPER-Circuit Synthesis
Opposite-Phase Clock Tree for Peak Current Reduction
Yow-Tyng NIEH  Shih-Hsu HUANG  Sheng-Yu HSU  
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pp.2736-2742  PAPER-Circuit Synthesis
Low Area Pipelined Circuits by the Replacement of Registers with Delay Elements
Bakhtiar Affendi ROSDI  Atsushi TAKAHASHI  
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pp.2743-2751  PAPER-Circuit Synthesis
A Relocation Method for Circuit Modifications
Kunihiko YANAGIBASHI  Yasuhiro TAKASHIMA  Yuichi NAKAMURA  
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pp.2752-2761  PAPER-Logic Synthesis and Verification
Design Method for Numerical Function Generators Using Recursive Segmentation and EVBDDs
Shinobu NAGAYAMA  Tsutomu SASAO  Jon T. BUTLER  
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pp.2762-2769  PAPER-Logic Synthesis and Verification
BDD Representation for Incompletely Specified Multiple-Output Logic Functions and Its Applications to the Design of LUT Cascades
Munehiro MATSUURA  Tsutomu SASAO  
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pp.2770-2777  PAPER-Logic Synthesis and Verification
Timing-Constrained Area Minimization Algorithm for Parallel Prefix Adders
Taeko MATSUNAGA  Yusuke MATSUNAGA  
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pp.2778-2789  PAPER-Logic Synthesis and Verification
Satisfiability Checking for Logic with Equality and Uninterpreted Functions under Equivalence Constraints
Hiroaki KOZAWA  Kiyoharu HAMAGUCHI  Toshinobu KASHIWABARA  
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pp.2790-2799  PAPER-System Level Design
Scheduling Methods for Asynchronous Circuits with Bundled-Data Implementations Based on the Approximation of Start Times
Hiroshi SAITO  Naohiro HAMADA  Nattha JINDAPETCH  Tomohiro YONEDA  Chris MYERS  Takashi NANYA  
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pp.2800-2809  PAPER-System Level Design
Generation of Pack Instruction Sequence for Media Processors Using Multi-Valued Decision Diagram
Hiroaki TANAKA  Yoshinori TAKEUCHI  Keishi SAKANUSHI  Masaharu IMAI  Hiroki TAGAWA  Yutaka OTA  Nobu MATSUMOTO  
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pp.2810-2817  PAPER-System Level Design
Efficient Memory Utilization for High-Speed FPGA-Based Hardware Emulators with SDRAMs
Kohei HOSOKAWA  Katsunori TANAKA  Yuichi NAKAMURA  
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pp.2818-2825  PAPER-System Level Design
High-Efficiency VLSI Architecture Design for Motion-Estimation in H.264/AVC
Chun-Lung HSU  Mean-Hom HO  
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Regular Section

pp.2826-2834  PAPER-Engineering Acoustics
An Approach to Solve Local Minimum Problem in Sound Source and Microphone Localization
Kazunori KOBAYASHI  Ken'ichi FURUYA  Yoichi HANEDA  Akitoshi KATAOKA  
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pp.2835-2845  PAPER-Digital Signal Processing
A Distortion-Free Learning Algorithm for Feedforward Multi-Channel Blind Source Separation
Akihide HORITA  Kenji NAKAYAMA  Akihiro HIRANO  
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pp.2846-2852  PAPER-Analog Signal Processing
An Algorithm to Improve the Performance of M-Channel Time-Interleaved A-D Converters
Koji ASAMI  
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pp.2853-2862  PAPER-VLSI Design Technology and CAD
Function-Level Partitioning of Sequential Programs for Efficient Behavioral Synthesis
Yuko HARA  Hiroyuki TOMIYAMA  Shinya HONDA  Hiroaki TAKADA  Katsuya ISHII  
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pp.2863-2876  PAPER-Numerical Analysis and Optimization
`Adaptive Link Adjustment' Applied to the Fixed Charge Transportation Problem
Sang-Moon SOAK  
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pp.2877-2883  PAPER-Numerical Analysis and Optimization
Kalman-Filter Based Estimation of Electric Load Composition with Non-ideal Transformer Modeling
Soon LEE  Seung-Mook BAEK  Jung-Wook PARK  Young-Hyun MOON  
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pp.2884-2890  PAPER-Numerical Analysis and Optimization
A Parallel Algorithm for NMNF Problems with a Large Number of Capacity Constraints
Shieh-Shing LIN  
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pp.2891-2902  PAPER-Reliability, Maintainability and Safety Analysis
Discrete Program-Size Dependent Software Reliability Assessment: Modeling, Estimation, and Goodness-of-Fit Comparisons
Shinji INOUE  Shigeru YAMADA  
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pp.2903-2907  PAPER-Information Security
The Vanstone-Zuccherato Schemes Revisited
Naoki KANAYAMA  Shigenori UCHIYAMA  
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pp.2908-2915  PAPER-Information Security
Improved MACs from Differentially-Uniform Permutations
Kazuhiko MINEMATSU  Toshiyasu MATSUSHIMA  
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pp.2916-2929  PAPER-Neural Networks and Bioengineering
Group-Linking Method: A Unified Benchmark for Machine Learning with Recurrent Neural Network
Tsungnan LIN  C. Lee GILES  
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pp.2930-2938  PAPER-Neural Networks and Bioengineering
An Improved Clonal Selection Algorithm and Its Application to Traveling Salesman Problems
Shangce GAO  Zheng TANG  Hongwei DAI  Jianchen ZHANG  
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pp.2939-2944  LETTER-Engineering Acoustics
Robust Source Separation with Simple One-Source-Active Detection
Yijing CHU  Heping DING  Xiaojun QIU  
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pp.2945-2948  LETTER-Digital Signal Processing
A Class of Cocyclic Quasi Jacket Block Matrix
Moon Ho LEE  Subash Shree POKHREL  Wen Ping MA  
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pp.2949-2951  LETTER-Digital Signal Processing
A Digital Image Watermarking Method Using Interval Arithmetic
Teruya MINAMOTO  Mitsuaki YOSHIHARA  Satoshi FUJII  
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pp.2952-2956  LETTER-Digital Signal Processing
Fast Parameter Selection Algorithm for Linear Parametric Filters
Akira TANAKA  Masaaki MIYAKOSHI  
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pp.2957-2961  LETTER-Systems and Control
Covariance Control for Bilinear Stochastic Systems via Sliding Mode Control Concept
Koan-Yuh CHANG  Tsung-Lin CHENG  
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pp.2962-2964  LETTER-Information Security
Security Analysis of Zhu-Bao's Verifiably Committed Signature
Dae Hyun YUM  Pil Joong LEE  
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pp.2965-2970  LETTER-Information Theory
A Note on the ε-Overflow Probability of Lossless Codes
Ryo NOMURA  Toshiyasu MATSUSHIMA  Shigeichi HIRASAWA  
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pp.2971-2974  LETTER-Communication Theory and Signals
An Effective SLM-PRSC Hybrid Scheme for OFDM PAPR Reduction
Seungwoo HAN  Suckchel YANG  Yoan SHIN  
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pp.2975-2978  LETTER-Communication Theory and Signals
Performance Bound for Finite-Length LDPC Coded Modulation
Huy G. VU  Ha H. NGUYEN  David E. DODDS  
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pp.2979-2984  LETTER-Image
A Hybrid Image Coder Based on SPIHT Algorithm with Embedded Block Coding
Tze-Yun SUNG  Hsi-Chin HSIN  
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pp.2985-2988  LETTER-Concurrent Systems
State Machines as Inductive Types
Kazuhiro OGATA  Kokichi FUTATSUGI  
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